Datasheet
RL78/L12 CHAPTER 1 OUTLINE
R01UH0330EJ0200 Rev.2.00 17
Dec 13, 2013
1.6 Outline of Functions
Caution This outline describes the functions at the time when Peripheral I/O redirection register (PIOR) is set
to 00H.
(1/2)
Item 32-pin 44-pin 48-pin 52-pin 64-pin
R5F10RBx R5F10RFx R5F10RGx R5F10RJx R5F10RLx
Code flash memory (KB) 8 to 32 8 to 32 8 to 32 8 to 32 16, 32
Data flash memory (KB) 2 2 2 2 2
RAM (KB) 1, 1.5
Note 1
1, 1.5
Note 1
1, 1.5
Note 1
1, 1.5
Note 1
1, 1.5
Note 1
Memory space 1 MB
Main
system
clock
High-speed system clock X1 (crystal/ceramic) oscillation, external main system clock input (EXCLK)
1 to 20 MHz: V
DD = 2.7 to 5.5 V, 1 to 8 MHz: VDD = 1.8 to 2.7 V, 1 to 4 MHz: VDD =
1.6 to 1.8 V
High-speed on-chip
oscillator clock
HS (high-speed main) operation: 1 to 24 MHz (VDD = 2.7 to 5.5 V),
HS (high-speed main) operation: 1 to 16 MHz (V
DD = 2.4 to 5.5 V),
LS (low-speed main) operation: 1 to 8 MHz (V
DD = 1.8 to 5.5 V),
LV (low-voltage main) operation: 1 to 4 MHz (V
DD = 1.6 to 5.5 V)
Subsystem clock
−
XT1 (crystal) oscillation , external subsystem clock input (EXCLKS)
32.768 kHz (TYP.): V
DD = 1.6 to 5.5 V
Low-speed on-chip oscillator clock Internal oscillation
15 kHz (TYP.): V
DD = 1.6 to 5.5 V
General-purpose register 8 bits × 32 registers (8 bits × 8 registers × 4 banks)
Minimum instruction execution time 0.04167
μ
s (High-speed on-chip oscillator clock: fIH = 24 MHz operation)
0.05
μ
s (High-speed system clock: fMX = 20 MHz operation)
30.5
μ
s (Subsystem clock: fSUB = 32.768 kHz operation)
Instruction set • Data transfer (8/16 bits)
• Adder and subtractor/logical operation (8/16 bits)
• Multiplication (8 bits × 8 bits)
• Rotate, barrel shift, and bit manipulation (Set, reset, test, and Boolean
operation), etc.
Total number of I/O port pins and
pins dedicated to drive an LCD
28 40 44 48 58
I/O
port
Total 20 29 33 37 47
CMOS I/O 15 22 26 30 39
CMOS input 3 5 5 5 5
CMOS output
− − − −
1
N-ch open-drain I/O
(EV
DD tolerance)
2 2 2 2 2
Pins dedicated to drive an LCD 8 11 11 11 11
LCD controller/driver Internal voltage boosting method, capacitor split method, and external resistance
division method are switchable.
Segment signal output 13
22 (18)
Note 2
26 (22)
Note 2
30 (26)
Note 2
39 (35)
Note 2
Common signal output 4
4 (8)
Note 2
Notes 1. In the case of the 1 KB, and 1.5 KB, this is 630 bytes when the self-programming function and data
flash function is used. (For details, see CHAPTER 3 CPU ARCHITECTURE)
2. The values in parentheses are the number of signal outputs when 8 com is used.
<R>
<R>