Datasheet

RL78/L12 CHAPTER 11 A/D CONVERTER
R01UH0330EJ0200 Rev.2.00 358
Dec 13, 2013
Figure 11-15. Conversion Operation of A/D Converter (Software Trigger Mode)
1 is written to ADCS
ADCS
Sampling
time
Conversion
start time
A
/D converter
operation
Conversion
standby
Sampling
Conversion
start
A/D conversion
Conversion
standby
Conversion
result
Conversion
result
Undefined
SAR
ADCR
INT
AD
Conversion time
In one-shot conversion mode, the ADCS bit is automatically cleared to 0 after completion of A/D conversion.
In sequential conversion mode, A/D conversion operations proceed continuously until the software clears bit 7 (ADCS)
of the A/D converter mode register 0 (ADM0) to 0.
Writing to the analog input channel specification register (ADS) during A/D conversion interrupts the current conversion
after which A/D conversion of the analog input specified by the ADS register proceeds. Data from the A/D conversion that
was in progress are discarded.
Reset signal generation clears the A/D conversion result register (ADCR, ADCRH) to 0000H or 00H.
<R>
<R>