Datasheet

RL78/L12 CHAPTER 11 A/D CONVERTER
R01UH0330EJ0200 Rev.2.00 352
Dec 13, 2013
11.3.5 10-bit A/D conversion result register (ADCR)
This register is a 16-bit register that stores the A/D conversion result. The lower 6 bits are fixed to 0. Each time A/D
conversion ends, the conversion result is loaded from the successive approximation register (SAR). The higher 8 bits of the
conversion result are stored in FFF1FH and the lower 2 bits are stored in the higher 2 bits of FFF1EH
Note
.
The ADCR register can be read by a 16-bit memory manipulation instruction.
Reset signal generation clears this register to 0000H.
Note If the A/D conversion result is outside the range specified by using the A/D conversion comparison function (the
value specified by the ADRCK bit of the ADM2 register and ADUL/ADLL registers; see Figure 11-8), the result
is not stored.
Figure 11-9. Format of 10-bit A/D Conversion Result Register (ADCR)
Symbol
Address: FFF1FH, FFF1EH After reset: 0000H R
FFF1FH FFF1EH
000000
ADCR
Cautions 1. When writing to the A/D converter mode register 0 (ADM0), analog input channel
specification register (ADS), and A/D port configuration register (ADPC), the contents of
the ADCR register may become undefined. Read the conversion result following
conversion completion before writing to the ADM0, ADS, and ADPC registers. Using
timing other than the above may cause an incorrect conversion result to be read.
2. When 8-bit resolution A/D conversion is selected (when the ADTYP bit of A/D converter
mode register 2 (ADM2) is 1) and the ADCR register is read, 0 is read from the lower two
bits (ADCR1 and ADCR0).
3. When the ADCR register is accessed in 16-bit units, the higher 10 bits of the conversion
result are read in order starting at bit 15.