Datasheet
RL78/L12 CHAPTER 11 A/D CONVERTER
R01UH0330EJ0200 Rev.2.00 347
Dec 13, 2013
Table 11-3. A/D Conversion Time Selection (4/4)
(4) When there is no stabilization wait time
Low-voltage mode 1, 2
Note 1
(hardware trigger wait mode
Note 2
)
A/D Converter Mode Register 0
(ADM0)
Mode
Conversion
Clock (f
AD
)
Number of
Stabilization
Wait Cock
Number of
Conversion
Clock
Cycles
Note 9
Stabilization
Wait Cock
+
Conversion
Time
Conversion Time Selection
1.6 V ≤ VDD ≤ 5.5 V Note 3 Note 4 Note 5
FR2 FR1 FR0 LV1 LV0 fCLK =
1 MHz
fCLK =
4 MHz
fCLK =
8 MHz
fCLK =
16 MHz
fCLK =
24 MHz
0 0 0 0 0 Low
voltage
1
fCLK/64 2 fAD
19 f
AD
(number
of
sampling
clock
cycles:
7 f
AD
)
1344/fCLK
Setting
prohibited
Setting
prohibited
Setting
prohibited
84
μ
s 56
μ
s
0 0 1 fCLK/32 672/fCLK 84
μ
s 42
μ
s 28
μ
s
0 1 0 fCLK/16 336/fCLK 84
μ
s 42
μ
s 21
μ
s 14
μ
s
0 1 1 fCLK/8 168/fCLK
42
μ
s
Note 8
21
μ
s 10.5
μ
s
Note 7
7
μ
s
1 0 0 fCLK/6 126/fCLK
31.25
μ
s
Note 8
15.75
μ
s
Note 7
7.875
μ
s
Note 7
5.25
μ
s
1 0 1 fCLK/5 105/fCLK
105
μ
s 26.25
μ
s
Note 8
13.125
μ
s
Note 7
6.5625
μ
s
Note 7
4.375
μ
s
1 1 0 fCLK/4 84/fCLK
84
μ
s 21
μ
s
Note 8
10.5
μ
s
Note 7
5.25
μ
s
Note 7
3.5
μ
s
Note 6
1 1 1 fCLK/2 42/fCLK
42
μ
s
Note 8
10.5
μ
s
Note 7
5.25
μ
s
Note 7
2.625
μ
s
Note 6
Setting
prohibited
0 0 0 0 1 Low
voltage
2
fCLK/64 2 fAD
17 f
AD
(number
of
sampling
clock
cycles:
5 f
AD
)
1216/fCLK
Setting
prohibited
Setting
prohibited
Setting
prohibited
76
μ
s 50.6667
μ
s
0 0 1 fCLK/32 608/fCLK 76
μ
s 38
μ
s 25.3333
μ
s
0 1 0 fCLK/16 304/fCLK 76
μ
s 38
μ
s 19
μ
s 12.6667
μ
s
0 1 1 fCLK/8 152/fCLK
38
μ
s
Note 8
19
μ
s 9.5
μ
s
Note 7
6.3333
μ
s
1 0 0 fCLK/6 114/fCLK
28.5
μ
s
Note 8
14.25
μ
s
Note 7
7.125
μ
s
Note7
4.75
μ
s
1 0 1 fCLK/5 96/fCLK
96
μ
s 23.75
μ
s
Note 8
12
μ
s
Note 7
5.938
μ
s
Note 7
4.0
μ
s
1 1 0 fCLK/4 76/fCLK
76
μ
s 19
μ
s
Note 8
9.5
μ
s
Note 7
4.75
μ
s
Note 7
3.1667
μ
s
Note 6
1 1 1 fCLK/2 38/fCLK
38
μ
s
Note 8
9.5
μ
s
Note 7
4.75
μ
s
Note 7
2.375
μ
s
Note 6
Setting
prohibited
Notes 1. This mode is prohibited when using the temperature sensor
2. For the second and subsequent conversion in sequential conversion mode, the conversion start time and
stabilization wait time for A/D power supply do not occur after a hardware trigger is detected (see table 12-3
(2/4)).
3. 1.8 V ≤ V
DD ≤ 5.5 V
4. 2.4 V ≤ V
DD ≤ 5.5 V
5. 2.7 V ≤ V
DD ≤ 5.5 V
6. Setting prohibited when VDD < 3.6 V.
7. Setting prohibited when V
DD< 2.7 V.
8. Setting prohibited when V
DD < 1.8 V.
9. These are the numbers of clock cycles when conversion is with 10-bit resolution. When eight-bit resolution is
selected, the values are shorter by two cycles of the conversion clock (f
AD).
Cautions 1. The A/D conversion time must also be within the relevant range of conversion times (t
CONV)
described in 30.6.1 A/D converter characteristics or 31.6.1 A/D converter characteristics.
2. When rewriting the FR2 to FR0, LV1, and LV0 bits to other than the same data, make sure that
conversion has stopped (ADCS = 0, ADCE = 0).
<R>
<R>