Datasheet

RL78/L12 CHAPTER 11 A/D CONVERTER
R01UH0330EJ0200 Rev.2.00 346
Dec 13, 2013
Table 11-3. A/D Conversion Time Selection (3/4)
(3) When there is stabilization wait time
Normal mode 1, 2 (hardware trigger wait mode
Note 1
)
A/D Converter Mode Register 0
(ADM0)
Mode
Conversion
Clock (f
AD )
Number of
Stabilization
Wait Cock
Number of
Conversion
Clock
Cycles
Note 4
Stabilization
Wait Cock
+
Conversion
Time
Conversion Time Selection
2.7 V ≤ VDD ≤ 5.5 V
FR2 FR1 FR0 LV1 LV0 fCLK =
1 MHz
fCLK =
4 MHz
fCLK =
8 MHz
fCLK =
16 MHz
fCLK =
24 MHz
0 0 0 0 0 Normal
1
fCLK/64 8 fAD 19 f AD
(number
of
sampling
clock
cycles:
7 f
AD )
1728/fCLK Setting
prohibited
Setting
prohibited
Setting
prohibited
108 μ s
72
μ s
0 0 1 fCLK/32 864/fCLK 108 μ s
54
μ s 36 μ s
0 1 0 fCLK/16 432/fCLK 108 μ s
54
μ s 27 μ s 18 μ s
0 1 1 fCLK/8 216/fCLK
54 μ s 27 μ s 13.5 μ s 9 μ s
1 0 0 fCLK/6 162/fCLK
40.5 μ s 20.25 μ s 10.125 μ s 6.75 μ s
1 0 1 fCLK/5 135/fCLK 135 μ s 33.75 μ s 16.875 μ s 8.4375 μ s 5.625 μ s
1 1 0 fCLK/4 108/fCLK 108 μ s 27 μ s 13.5 μ s 6.75 μ s 4.5 μ s
1 1 1 fCLK/2 54/fCLK 54 μ s 13.5 μ s 6.75 μ s 3.375 μ s
Notes 3
Setting
prohibited
0 0 0 0 1 Normal
2
fCLK/64 8 fAD 17 f AD
(number
of
sampling
clock
cycles:
5 f
AD )
1600/fCLK Setting
prohibited
Setting
prohibited
Setting
prohibited
100 μ s 66.6667 μ s
0 0 1 fCLK/32 800/fCLK 100 μ s 50 μ s 33.3333 μ s
0 1 0 fCLK/16 400/fCLK 100 μ s 50 μ s 25 μ s 16.6667 μ s
0 1 1 fCLK/8 200/fCLK 50 μ s 25 μ s 12.5 μ s 8.3333 μ s
1 0 0 fCLK/6 150/fCLK 37.5 μ s 18.75 μ s 9.375 μ s 6.25 μ s
1 0 1 fCLK/5 125/fCLK 125 μ s 31.25 μ s 15.625 μ s 7.8125 μ s 5.2083 μ s
1 1 0 fCLK/4 100/fCLK 100 μ s 25 μ s 12.5 μ s 6.25 μ s 4.1667 μ s
Notes 2, 3
1 1 1 fCLK/2 50/fCLK 50 μ s 12.5 μ s 6.25 μ s 3.125 μ s
Notes 2, 3
Setting
prohibited
Notes 1. For the second and subsequent conversion in sequential conversion mode, the conversion start time and
stabilization wait time for A/D power supply do not occur after a hardware trigger is detected (see table 12-3
(1/4)).
2. Setting prohibited when V
DD < 3.6 V.
3. This value is prohibited when using the temperature sensors.
4. These are the numbers of clock cycles when conversion is with 10-bit resolution. When eight-bit resolution is
selected, the values are shorter by two cycles of the conversion clock (f
AD).
Cautions 1. The A/D conversion time must also be within the relevant range of conversion times (t
CONV)
described in 30.6.1 A/D converter characteristics or 31.6.1 A/D converter characteristics.
2. When rewriting the FR2 to FR0, LV1, and LV0 bits to other than the same data, make sure that
conversion has stopped (ADCS = 0, ADCE = 0).
3. The above conversion time does not include conversion state time. Conversion state time add in
the first conversion. Select conversion time, taking clock frequency errors into consideration.
4. When hardware trigger wait mode, specify the conversion time, including the stabilization wait time
from the hardware trigger detection.
Remark f
CLK: CPU/peripheral hardware clock frequency
<R>
<R>