Datasheet

RL78/L12 CHAPTER 9 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER
R01UH0330EJ0200 Rev.2.00 325
Dec 13, 2013
9.3.3 Port mode registers 5, 14 (PM5, PM14)
These registers set input/output of port 5, 14 in 1-bit units.
When using the P50/INTP5/SEG7/(PCLBUZ0), P140/PCLBUZ0/TO00/SEG27 and P141/PCLBUZ1/TI00/SEG26 pins
for clock output and buzzer output, clear PM50, PM140 and PM141 bits and the output latches of P50, P140 and P141 to
0.
The PM5 and PM14 registers can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets these registers to FFH.
Figure 9-4. Format of Port Mode Registers 5, 14 (PM5, PM14)
Address: FFF25H After reset: FFH R/W
Symbol 7 6 5 4 3 2 1 0
PM5 1 1 1 PM54 PM53 PM52 PM51 PM50
Address: FFF2EH After reset: FFH R/W
Symbol 7 6 5 4 3 2 1 0
PM14 PM147 PM146 PM145 PM144 PM143 PM142 PM141 PM140
PMmn Pmn pin I/O mode selection (mn = 50 to 54, 140 to 147)
0 Output mode (output buffer on)
1 Input mode (output buffer off)