Datasheet

RL78/L12 CHAPTER 9 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER
R01UH0330EJ0200 Rev.2.00 323
Dec 13, 2013
9.3.2 Clock output select registers n (CKSn)
These registers set output enable/disable for clock output or for the buzzer frequency output pin (PCLBUZn), and set
the output clock.
Select the clock to be output from the PCLBUZn pin by using the CKSn register.
The CKSn register are set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears these registers to 00H.
Figure 9-3. Format of Clock Output Select Register n (CKSn)
Address: FFFA5H (CKS0), FFFA6H (CKS1) After reset: 00H R/W
Symbol <7> 6 5 4 3 2 1 0
CKSn PCLOEn 0 0 0 CSELn CCSn2 CCSn1 CCSn0
PCLOEn PCLBUZn pin output enable/disable specification
0 Output disable (default)
1 Output enable
CSELn CCSn2 CCSn1 CCSn0 PCLBUZn pin output clock selection
f
MAIN =
5 MHz
fMAIN =
10 MHz
fMAIN =
20 MHz
fMAIN =
24 MHz
0 0 0 0 fMAIN 5 MHz 10 MHz
Note 1
Setting
prohibited
Note 1
Setting
prohibited
Note 1
0 0 0 1 fMAIN/2 2.5 MHz 5 MHz 10 MHz
Note 1
12 MHz
Note 1
0 0 1 0 fMAIN/2
2
1.25 MHz 2.5 MHz 5 MHz 6 MHz
0 0 1 1 fMAIN/2
3
625 kHz 1.25 MHz 2.5 MHz 3 MHz
0 1 0 0 fMAIN/2
4
312.5 kHz 625 kHz 1.25 MHz 1.5 MHz
0 1 0 1 fMAIN/2
11
2.44 kHz 4.88 kHz 9.76 kHz 11.7 kHz
0 1 1 0 fMAIN/2
12
1.22 kHz 2.44 kHz 4.88 kHz 5.86 kHz
0 1 1 1 fMAIN/2
13
610 Hz 1.22 kHz 2.44 kHz 2.93 kHz
1 0 0 0
f
SUB
Note
2
32.768 kHz
1 0 0 1 f SUB /2
Note 2
16.384 kHz
1 0 1 0 f SUB /2
2 Note 2
8.192 kHz
1 0 1 1 f SUB /2
3 Note 2
4.096 kHz
1 1 0 0 f SUB /2
4 Note 2
2.048 kHz
1 1 0 1 f SUB /2
5 Note 2
1.024 kHz
1 1 1 0 f SUB /2
6 Note 2
512 Hz
1 1 1 1 f SUB /2
7 Note 2
256 Hz
(Notes, Cautions, and Remarks are listed on the next page.)