Datasheet

RL78/L12 CHAPTER 9 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER
R01UH0330EJ0200 Rev.2.00 320
Dec 13, 2013
Figure 9-1. Block Diagram of Clock Output/Buzzer Output Controller
f MAIN
f SUB
Note 1
PCLOE0 0 0 0
PCLOE0
5
3
PCLBUZ0
Note 2
/TO00/
SEG27/P140
PCLBUZ1
Note 2
/TI00/
SEG26/P141
CSEL0 CCS02 CCS01 CCS00
PM141
PM140
PCLOE1 0 0 0 CSEL1 CCS12 CCS11 CCS10
8
PCLOE1
8
f MAIN /2
11
to f MAIN /2
13
Clock/buzzer
controller
Internal bus
Clock output select register 1 (CKS1)
Prescaler
Prescaler
Selector
Selector
Clock/buzzer
controller
Output latch
(P141)
Internal bus
Clock output select register 0 (CKS0)
Output latch
(P140)
f MAIN /2
11
to f MAIN /2
13
f MAIN to f MAIN /2
4
f MAIN to f MAIN /2
4
f SUB to f SUB /2
7
f SUB to f SUB /2
7
Notes 1. Do not select f
SUB as the clock output from the clock output/buzzer output controller when the WUTMMCK0
bit of the OSMC register is set to 1.
2. For output frequencies available from PCLBUZ0 and PCLBUZ1, refer 30.4 AC Characteristics.
Remark PCLBUZ0 pin in above diagram shows the information of 48- to 64-pins products with PIOR1 = 0.
In other cases, the name of pins, output latches (Pxx) and PMxx should be read differently (xx = 50).