Datasheet

RL78/L12 CHAPTER 1 OUTLINE
R01UH0330EJ0200 Rev.2.00 12
Dec 13, 2013
1.5 Block Diagram
1.5.1 32-pin products
ch2
ch3
ch0
ch1
ch4
ch5
ch6
ch7
PORT 2 P20, P212
PORT 3 P30
PORT 1 P10 to P178
PORT 4 P40
VOLTAGE
REGULATOR
REGC
INTERRUPT
CONTROL
RAM
POWER ON RESET/
VOLTAGE
DETECTOR
POR/LVD
CONTROL
RESET CONTROL
SYSTEM
CONTROL
RESET
X1/P121
X2/EXCLK/P122
HIGH-SPEED
ON-CHIP
OSCILLATOR
ON-CHIP DEBUG
TOOL0/P40
TIMER ARRAY
UNIT0 (8ch)
TI02/TO02/P17
(TI02/TO02/P12)
2
INTP0/P137
INTP1/P15(INTP1/P10),
INTP2/P16(INTP2/P11)
TO00/P140
TI00/P13
BCD
ADJUSTMENT
V
SS TOOLRxD/P11,
TOOLTxD/P12
V
DD
SERIAL ARRAY
UNIT0 (2ch)
UART0
RxD0/P11
TxD0/P12
CSI01
SCK01/P15
SO01/P17
SI01/P16
SCK00/P10
SO00/P12
SI00/P11
CSI00
SCLA0/P60
SERIAL
INTERFACE IICA0
SDAA0/P61
MULTIPLIER&
DIVIDER,
MULITIPLY-
ACCUMULATOR
KEY RETURN
3
KR0/P12 to KR2/P10
DIRECT MEMORY
ACCESS
CONTROL
PORT 6 P60, P61
2
BUZZER OUTPUT
PCLBUZ0/P140
CLOCK OUTPUT
CONTROL
TI01/TO01/P30
A/D CONVERTER
2 ANI0/P20, ANI1/P21
AV REFP /P20
AV
REFM /P21
2 ANI18/P13, ANI19/P14
PORT 13 P137
WINDOW
WATCHDOG
TIMER
RL78
CPU
CORE
CODE FLASH MEMORY
DATA FLASH MEMORY
PORT 12
P121, P122
2
P126, P127
2
LCD
CONTROLLER/
DRIVER
COM0 to COM3
13
SEG0, SEG4 to SEG6,
SEG19 to SEG21,
SEG27 to SEG32
4
V L1 , V L2 , V L4
CAPH
CAPL
RAM SPACE
FOR LCD DATA
TI07/TO07/P10
KR3/P140
PORT 14 P140
REAL-TIME
CLOCK
LOW-SPEED
ON-CHIP
OSCILLATOR
12- BIT INTERVAL
TIMER
CRC
Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection
register (PIOR)
<R>