Datasheet

RL78/L12 CHAPTER 6 TIMER ARRAY UNIT
R01UH0330EJ0200 Rev.2.00 283
Dec 13, 2013
Figure 6-85. Procedure for Setting Remote Control Output (2/2)
Software Operation Hardware Status
Operation
start
The cycle of the mask waveform (start code) and its high-
level width are set.
TDR02 = The cycle of the mask waveform - 1
TDR03 = High-level width of the mask waveform
The cycle of the carrier waveform and its high-level width
are set.
TDR06 = The cycle of the carrier waveform - 1
TDR07 = High-level width of the carrier waveform
The TSmn bit (master), and TSmp (slave) bits of timer
channel start register m (TSm) are set to 1 at the same
time.
The TSmn and TSmp bits automatically return to 0
because they are trigger bits.
TEmn = 1, TEmp, TEmq = 1
When the master channel starts counting, INTTM02 is
generated. Triggered by this interrupt, the slave
channel also starts counting.
During
operation
The setting of the TMRmn and TMRmp registers, and the
TOMmn, TOMmp, TOLmn, and TOLmp bits must not be
changed.
The TCRmn and TCRmp registers can always be read.
Wait for an interrupt signal (INTTM02)
Last code bit?
• If it is not the end code bit, the cycle and high-level
width of the next mask waveform are specified.
TDR02 = The cycle of the mask waveform - 1
TDR03 = High-level width of the mask waveform
Caution Setting must finish before the TCR02
value reaches 0000H.
• If it is the end code bit, the operation stops
TO03 outputs the mask waveform and TO07 outputs the
carrier waveform in accordance with the settings of the
cycle and high-level width.
The P32/TO03 pin outputs the result of ANDing the TO03
and TO07 outputs (a remote control output (carrier
waveform) until TCR03 reaches 0000H; a low-level
remote control output until TCR02 reaches 0000H and
TCR03 equals FFFFH).
Interrupt signal (INTTM02) to be generated at TCR02 =
0000H.
Operation
stop
The duty of the mask waveform is set to 0%.
TDR02 = 0000H
TDR03 is setting not required.
Caution Setting must finish before the TCR02
value reaches 0000H.
Wait for an interrupt signal (INTTM02)
The TTmn bit (master) and TTmp (slave) bits are set to 1
at the same time.
The TTmn and TTmp bits automatically return to 0
because they are trigger bits.
The P32/TO03 pin outputs the result of ANDing the
TO03 and TO07 outputs (a remote control output (carrier
waveform) until TCR03 reaches 0000H; a low-level
remote control output after TCR03 reaches 0000H).
Interrupt signal (INTTM02) to be generated at TCR02 =
0000H.
TEmn, TEmp, TEmq = 0, and count operation stops.
The TOEmn and TOEmp bits are cleared to 0 and TOmn
and TOmp bits are cleared to 0
Note
.
The TOmp pin is clear to low-level.
Transmission
restart
To resume transmission, set the TOEmp bit of timer
output enable register m (TOEm) to 1. (The TOEmn bit
remains 0.)
Note If these bits are not used by any TAU channel, clock supply may be stopped by clearing the TAU0EN bit of
peripheral enable register 0 (PER0) to 0. In this case, to resume transmission, the settings for transmission must
be re-specified after the power is turned on.
Remark m: Unit number (m = 0), n: Master channel number (n = 2, 6)
p: Slave channel number (p = 3, 7)
(When mask waveform: n = 2, n = 3 ; When carrier waveform: n = 6, p = 7)
Operation is resumed.