Datasheet

RL78/L12 CHAPTER 6 TIMER ARRAY UNIT
R01UH0330EJ0200 Rev.2.00 213
Dec 13, 2013
(2) When valid edge of input signal input from the TImn pin is selected (CCSmn = 1)
The count clock (fTCLK) is between fCLK to fCLK /2
15
by setting of timer clock select register m (TPSm). When a
divided f
CLK is selected, however, the count clock is not a signal which is simply divided fCLK by 2
m
, but a signal
which becomes high level for one period of f
CLK from its rising edge (m = 1 to 15).
Counting of timer count register mn (TCRmn) delayed by one period of fCLK from rising edge of the count clock,
because of synchronization with f
CLK. But, this is described as “counting at rising edge of the count clock”, as a
matter of convenience.
Figure 6-27. Timing of f
CLK and count clock (fTCLK) (When CCSmn = 1, noise filter unused)
<1> Setting TSmn bit to 1 enables the timer to be started and to become wait state for valid edge of input signal via
the TImn pin.
<2> The rise of input signal via the TImn pin is sampled by f
MCK.
<3> The edge is detected by the rising of the sampled signal and the detection signal (count clock) is output.
Remarks 1. : Rising edge of the count clock
: Synchronization, increment/decrement of counter
2. f
MCK: Operation clock of channel n
3. The waveform of the input signal to TImn pin of the input pulse interval measurement, the
measurement of high/low width of input signal, the delay counter, the one-shot pulse
output is the same as that shown in Figure 6-27.
f
MC
K
TSmn(Write)
TEmn
TImn input
<1>
<2>
Rising edge
detection signal (f
TCLK
)
Sampling wave
Edge detection
Edge detection
<3>