Datasheet
RL78/L12 CHAPTER 6 TIMER ARRAY UNIT
R01UH0330EJ0200 Rev.2.00 189
Dec 13, 2013
Figure 6-11. Format of Timer Clock Select register m (TPSm) (2/2)
Address: F01B6H, F01B7H After reset: 0000H R/W
Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TPSm 0 0
PRS
m31
PRS
m30
0 0
PRS
m21
PRS
m20
PRS
m13
PRS
m12
PRS
m11
PRS
m10
PRS
m03
PRS
m02
PRS
m01
PRS
m00
PRS
m21
PRS
m20
Selection of operation clock (CKm2)
Note
fCLK = 2 MHz fCLK = 5 MHz fCLK = 10 MHz fCLK = 20 MHz fCLK = 24 MHz
0 0 fCLK/2 1 MHz 2.5 MHz 5 MHz 10 MHz 12 MHz
0 1 fCLK/2
2
500 kHz 1.25 MHz 2.5 MHz 5 MHz 6 MHz
1 0 fCLK/2
4
125 kHz 312.5 kHz 625 MHz 1.25 MHz 1.5 MHz
1 1 fCLK/2
6
31.25 kHZ 78.1 kHz 156.2 kHz 312.5 kHz 375 MHz
PRS
m31
PRS
m30
Selection of operation clock (CKm3)
Note
fCLK = 2 MHz fCLK = 5 MHz fCLK = 10 MHz fCLK = 20 MHz fCLK = 24 MHz
0 0 fCLK/2
8
7.81 kHz 19.5 kHz 39.1 kHz 78.1 kHz 93.8 kHz
0 1 fCLK/2
10
1.95 kHz 4.88 kHz 9.76 kHz 19.5 kHz 23.4 kHz
1 0 fCLK/2
12
488 Hz 1.22 kHz 2.44 kHz 4.88 kHz 5.86 kHz
1 1 fCLK/2
14
122 HZ 305 Hz 610 Hz 1.22 kHz 1.46 kHz
Note When changing the clock selected for f
CLK (by changing the system clock control register (CKC)
value), stop timer array unit (TTm = 00FFH).
The timer array unit must also be stopped if the operating clock (f
MCK) specified by using the CKSmn0,
and CKSmn1 bits or the valid edge of the signal input from the TImn pin is selected as the count clock
(f
TCLK).
Caution Be sure to clear bits 15, 14, 11, 10 to “0”.
By using channels 1 and 3 in the 8-bit timer mode and specifying CKm2 or CKm3 as the operation clock, the
interval times shown in Table 6-4 can be achieved by using the interval timer function.
Table 6-4. Interval Times Available for Operation Clock CKSm2 or CKSm3
Clock Interval time (fCLK = 24 MHz)
10
μ
s
Note
100
μ
s
Note
1 ms
Note
10 ms
Note
CKm2 fCLK/2
√ − − −
fCLK/2
2
√ − − −
fCLK/2
4
√ √ − −
fCLK/2
6
√ √ − −
CKm3 fCLK/2
8
− √ √ −
fCLK/2
10
− √ √ −
fCLK/2
12
− − √ √
fCLK/2
14
− − √ √
Note The margin is within 5 %.
Remarks 1. f
CLK: CPU/peripheral hardware clock frequency
2. For details of a signal of f
CLK/2
j
selected with the TPSm register, see 6.5.1 Count clock (fTCLK).