Datasheet

RL78/L12 CHAPTER 6 TIMER ARRAY UNIT
R01UH0330EJ0200 Rev.2.00 188
Dec 13, 2013
Figure 6-11. Format of Timer Clock Select register m (TPSm) (1/2)
Address: F01B6H, F01B7H After reset: 0000H R/W
Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TPSm 0 0
PRS
m31
PRS
m30
0 0
PRS
m21
PRS
m20
PRS
m13
PRS
m12
PRS
m11
PRS
m10
PRS
m03
PRS
m02
PRS
m01
PRS
m00
PRS
mk3
PRS
mk2
PRS
mk1
PRS
mk0
Selection of operation clock (CKmk)
Note
(k = 0, 1)
fCLK = 2 MHz fCLK = 5 MHz fCLK = 10 MHz fCLK = 20 MHz fCLK = 24 MHz
0 0 0 0 fCLK 2 MHz 5 MHz 10 MHz 20 MHz 24 MHz
0 0 0 1 fCLK/2 1 MHz 2.5 MHz 5 MHz 10 MHz 12 MHz
0 0 1 0 fCLK/2
2
500 kHz 1.25 MHz 2.5 MHz 5 MHz 6 MHz
0 0 1 1 fCLK/2
3
250 kHz 625 kHz 1.25 MHz 2.5 MHz 3 MHz
0 1 0 0 fCLK/2
4
125 kHz 312.5 kHz 625 kHz 1.25 MHz 1.5 MHz
0 1 0 1 fCLK/2
5
62.5 kHz 156.2 kHz 312.5 kHz 625 kHz 750 kHz
0 1 1 0 fCLK/2
6
31.25 kHz 78.1 kHz 156.2 kHz 312.5 kHz 375 kHz
0 1 1 1 fCLK/2
7
15.62 kHz 39.1 kHz 78.1 kHz 156.2 kHz 187.5 kHz
1 0 0 0 fCLK/2
8
7.81 kHz 19.5 kHz 39.1 kHz 78.1 kHz 93.8 kHz
1 0 0 1 fCLK/2
9
3.91 kHz 9.76 kHz 19.5 kHz 39.1 kHz 46.9 kHz
1 0 1 0 fCLK/2
10
1.95 kHz 4.88 kHz 9.76 kHz 19.5 kHz 23.4 kHz
1 0 1 1 fCLK/2
11
976 Hz 2.44 kHz 4.88 kHz 9.76 kHz 11.7 kHz
1 1 0 0 fCLK/2
12
488 Hz 1.22 kHz 2.44 kHz 4.88 kHz 5.86 kHz
1 1 0 1 fCLK/2
13
244 Hz 610 Hz 1.22 kHz 2.44 kHz 2.93 kHz
1 1 1 0 fCLK/2
14
122 Hz 305 Hz 610 Hz 1.22 kHz 1.46 kHz
1 1 1 1 fCLK/2
15
61 Hz 153 Hz 305 Hz 610 Hz 732 Hz
Note When changing the clock selected for fCLK (by changing the system clock control register (CKC)
value), stop timer array unit (TTm = 00FFH).
Cautions 1. Be sure to clear bits 15, 14, 11, 10 to “0”.
2. If f
CLK (undivided) is selected as the operation clock (CKmk) and TDRnm is set to 0000H
(n = 0 or 1, m = 0 to 7), interrupt requests output from timer array units are not detected.
Remarks 1. f
CLK: CPU/peripheral hardware clock frequency
2. Waveform of the clock to be selected in the TPSm register which becomes high level for one
period of f
CLK from its rising edge (m = 1 to 15). For details, see 6.5.1 Count clock (fTCLK).