Datasheet

RL78/L12 CHAPTER 6 TIMER ARRAY UNIT
R01UH0330EJ0200 Rev.2.00 180
Dec 13, 2013
Figure 6-2. Internal Block Diagram of Channels 0, 2, 4, 6 of Timer Array Unit 0
PMxx
CKS0n
CCS0n
MAS
TER0n
STS0n2
STS0n1
STS0n0
MD0n2CIS0n1CIS0n0
MD0n3
MD0n1
MD0n0
OVF
0n
CK00
CK01
fMCK
f TCLK
Interrupt
controller
Output
controller
Output latch
(Pxx)
INTTM0n
(Timer interrupt)
TO0n
Timer status
register 0n (TSR0n)
Overflow
Timer data register 0n (TDR0n)
Timer counter register 0n (TCR0n)
Timer mode register 0n (TMR0n)
Channel n
Timer controller
Trigger
selection
Count clock
selection
Mode
selection
Slave/master
controller
Edge
detection
Operating
clock selection
TI0n
Input signal from the master channel
Note 1
Interrupt signal to the slave channel
Note2
Notes 1. Channels 2, 4, and 6 only
2. n = 2, 4, 6 only
Remark n = 0, 2, 4, 6
Figure 6-3. Internal Block Diagram of Channel 1 of Timer Array Unit 0
TO01
PMxx
CKS0CKS11 1 CCS01
SPLIT
01
STS01
2STS011 210DM010STS CIS011CIS010 MD013 MD011 MD010
OVF
01
INTTM01
(Timer interr
upt)
CK00
CK01
f MCK
f TCLK
CK02
CK03
INTTM01H
(Timer interr
upt)
Interrupt
controller
Output
controller
Output latch
(Pxx)
Timer status
register 01 (TSR01)
Overflow
Timer data register 01 (TDR01)
Timer counter register 01 (TCR01)
Timer mode register 01 (TMR01)
Channel 1
Timer controller
Tr ig g er
selection
Count clock
selection
Mode
selection
Edge
detection
Operating
clock selection
Input signal from the master channel
8-bit timer
controller
Mode
selection
Interrupt
controller
f SUB
f IL
TI01
Timer input select
register 0 (TIS0)
TIS2 TIS0TIS1
selector
<R>
<R>
<R>