Datasheet

RL78/L12 CHAPTER 6 TIMER ARRAY UNIT
R01UH0330EJ0200 Rev.2.00 179
Dec 13, 2013
Figure 6-1. Entire Configuration of Timer Array Unit (Example: 64-pin products)
Timer clock select register 0 (TPS0)
Peripheral enable
register 0
(PER0)
INTTM00
(Timer interr
upt)
TO01
TI00
TI02
TI03
TI04
TI06
TO00
TO02
TO03
TO04
TO05
TO06
INTTM02
INTTM03
INTTM04
INTTM05
INTTM06
INTTM07
TI07
TO07
INTTM01
INTTM03H
INTTM01H
2 2 4
4
f CLK
f CLK /2
0
- f CLK /2
15
TAU0EN
f CLK /2
1
, f CLK /2
2
,
f
CLK /2
4
,f CLK /2
6
,
f CLK /2
8
, f CLK /2
10
,
f
CLK /2
12
,f CLK /2
14
,
300SRP310SRP PRS012 PRS011 PRS010 PRS002 PRS001 PRS000PRS031 PRS030 PRS021 PRS020
SelectorSelector
rotceleSrotceleS
Prescaler
Channel 2
Channel 3
Channel 4
Channel 6
Channel 0
Channel 1
Channel 7
Timer input select
register 0 (TIS0)
f
SUB
f IL
TI01
TIS2 TIS0TIS1
Selector
Slave/master controller
Slave/master controller
Channel 5 (LIN-bus supported)
TI05
RxD0
(Serial input pin)
ISC1
Selector
Remark fSUB: Subsystem clock frequency
f
IL: Low-speed on-chip oscillator clock frequency
<R>