Datasheet

RL78/L12 CHAPTER 6 TIMER ARRAY UNIT
R01UH0330EJ0200 Rev.2.00 177
Dec 13, 2013
6.2 Configuration of Timer Array Unit
Timer array unit includes the following hardware.
Table 6-1. Configuration of Timer Array Unit
Item Configuration
Timer/counter Timer count register mn (TCRmn)
Register Timer data register mn (TDRmn)
Timer input
TI00 to TI07
Note 1
, RxD0 pin (for LIN-bus)
Timer output
TO00 to TO07
Note 1
, output controller
Control registers <Registers of unit setting block>
• Peripheral enable register 0 (PER0)
• Timer clock select register m (TPSm)
• Timer channel enable status register m (TEm)
• Timer channel start register m (TSm)
• Timer channel stop register m (TTm)
• Timer input select register 0 (TIS0)
• Timer output select register (TOS)
• Timer output enable register m (TOEm)
• Timer output register m (TOm)
• Timer output level register m (TOLm)
• Timer output mode register m (TOMm)
<Registers of each channel>
• Timer mode register mn (TMRmn)
• Timer status register mn (TSRmn)
• Input switch control register (ISC)
• Noise filter enable register 1 (NFEN1)
• Port mode control register (PMCxx)
Note 2
• Port mode register (PMxx)
Note 2
• Port register (Pxx)
Note 2
Notes 1. The presence or absence of timer I/O pins of channel 0 to 7 depends on the product. See Table 6-2
Timer I/O Pins provided in Each Product for details.
2. The Port mode control register (PMCxx), port mode registers (PMxx) and port registers (Pxx) to be set
differ depending on the product. For details, see 6.3.16 Port mode registers 1, 3 to 5, 14 (PM1, PM3 to
PM5, PM14).
Remark m: Unit number (m = 0), n: Channel number (n = 0 to 7)