Datasheet

RL78/L12 CHAPTER 5 CLOCK GENERATOR
R01UH0330EJ0200 Rev.2.00 144
Dec 13, 2013
Figure 5-7. Format of Peripheral Enable Register 0 (PER0) (2/2)
Address: F00F0H After reset: 00H R/W
Symbol <7> 6 <5> <4> 3 <2> 1 <0>
PER0 RTCEN 0 ADCEN IICA0EN 0 SAU0EN 0 TAU0EN
IICA0EN Control of serial interface IICA0 input clock supply
0
Stops input clock supply.
• SFR used by the serial interface IICA0 cannot be written.
• The serial interface IICA0 is in the reset status.
1
Enables input clock supply.
• SFR used by the serial interface IICA0 can be read and written.
SAU0EN Control of serial array unit 0 input clock supply
0
Stops input clock supply.
• SFR used by the serial array unit 0 cannot be written.
• The serial array unit 0 is in the reset status.
1
Enables input clock supply.
• SFR used by the serial array unit 0 can be read and written.
TAU0EN Control of timer array unit 0 input clock supply
0
Stops input clock supply.
• SFR used by timer array unit 0 cannot be written.
• Timer array unit 0 is in the reset status.
1
Enables input clock supply.
• SFR used by timer array unit 0 can be read and written.
Caution Be sure to clear the following bits 1, 3, and 6 to 0.