Datasheet

RL78/L12 APPENDIX A REVISION HISTORY
R01UH0330EJ0200 Rev.2.00 980
Dec 13, 2013
(2/10)
Edition
Description Chapter
Rev.1.00
Modification of description in 4.1 Port Functions
CHAPTER 4
PORT FUNCTIONS
Addition of caution to 4.3 Registers Controlling Port Function
Modification of Figure 4-2. Format of Port Register (64-pin products)
Modification of description and addition of caution to 4.3.3 Pull-up resistor option registers
(PUxx)
Addition of description in 4.3.5 Port output mode registers (POM1)
Addition of cautions 1 and 2 to Figure 4-6. Format of Port Mode Control Register
Modification of description in 4.3.8 Peripheral I/O redirection register (PIOR)
Modification of description in 4.4.1 (2) Input mode and 4.4.3 (2) Input mode
Modification of description in 4.4.4 Connecting to external device with different potential (1.8
V, 2.5 V, 3 V)
Addition of caution to 4.5 Settings of Port Mode Register, and Output Latch When Using
Alternate Function
Addition of 4.6.2 Notes on specifying the pin settings
Addition of 5.1 (1) <2> High-speed on-chip oscillator
CHAPTER 5
CLOCK
GENERATOR
Modification of Figure 5-1. Block Diagram of Clock Generator
Modification of cautions 1, 7 and addition of cautions 4 to 6 to Figure 5-2. Format of Clock
Operation Mode Control Register (CMC)
Deletion of cautions 1 to 4 and addition of cautions 1 to 3 in 5.3.8 High-speed on-chip
oscillator frequency select register (HOCODIV)
Modification of caution in Figure 5-12. Example of External Circuit of XT1 Oscillator
Modification of note 3 in Figure 5-14. Clock Generator Operation When Power Supply Voltage
Is Turned On
Modification of description of [Option byte setting] in 5.6.1 Example of setting high-speed on-
chip oscillator
Addition of description to 5.6.2 Example of setting X1 oscillation clock
Addition of description to Figure 5-15. CPU Clock Status Transition Diagram
Addition of description to Table 5-3. CPU Clock Transition and SFR Register Setting Examples
Modification and deletion of description in Table 5-4. Changing CPU Clock
Modification of remark 2 to 5.6.6 Time required for switchover of CPU clock and system clock
Modification of description in 6.1.1 (7) Delay counter
CHAPTER 6
TIMER ARRAY UNIT
Modification of caution in 6.1.2 (4) Remote control output function
Modification of Figure 6-2. Internal Block Diagram of Channels 0, 2, 4, 6 of Timer Array Unit 0
Addition of Figures 6-3 to 6-6
Modification of Table 6-3. Timer Count Register mn (TCRmn) Read Value in Various
Operation Modes
Modification of description in 6.2.2 Timer data register mn (TDRmn)
Modification of caution 1 in Figure 6-10. Format of Peripheral Enable Register 0 (PER0)
Modification of note and remark 2 and addition of caution 2 to Figure 6-11. Format of Timer
Clock Select register m (TPSm) (1/2)