Datasheet

Index-4
5.6.1 Example of setting high-speed on-chip oscillator ........................................................................... 155
5.6.2 Example of setting X1 oscillation clock ........................................................................................... 156
5.6.3 Example of setting XT1 oscillation clock ........................................................................................ 157
5.6.4 CPU clock status transition diagram ............................................................................................... 158
5.6.5 Condition before changing CPU clock and processing after changing CPU clock ......................... 164
5.6.6 Time required for switchover of CPU clock and system clock ........................................................ 166
5.6.7 Conditions before clock oscillation is stopped ................................................................................ 167
5.7 Resonator and Oscillator Constants ........................................................................................ 168
CHAPTER 6 TIMER ARRAY UNIT ...................................................................................................... 171
6.1 Functions of Timer Array Unit ................................................................................................... 173
6.1.1 Independent channel operation function ........................................................................................ 173
6.1.2 Simultaneous channel operation function ....................................................................................... 174
6.1.3 8-bit timer operation function (channels 1 and 3 only) .................................................................... 176
6.1.4 LIN-bus supporting function (channel 5 only) ................................................................................. 176
6.2 Configuration of Timer Array Unit ............................................................................................ 177
6.2.1 Timer count register mn (TCRmn) .................................................................................................. 182
6.2.2 Timer data register mn (TDRmn) .................................................................................................... 184
6.3 Registers Controlling Timer Array Unit .................................................................................... 185
6.3.1 Peripheral enable register 0 (PER0) ............................................................................................... 186
6.3.2 Timer clock select register m (TPSm) ............................................................................................ 187
6.3.3 Timer mode register mn (TMRmn) ................................................................................................. 190
6.3.4 Timer status register mn (TSRmn) ................................................................................................. 195
6.3.5 Timer channel enable status register m (TEm) ............................................................................... 196
6.3.6 Timer channel start register m (TSm) ............................................................................................. 197
6.3.7 Timer channel stop register m (TTm) ............................................................................................. 198
6.3.8 Timer input select register 0 (TIS0) ................................................................................................ 199
6.3.9 Timer output select register (TOS) ................................................................................................. 199
6.3.10 Timer output enable register m (TOEm) ....................................................................................... 200
6.3.11 Timer output register m (TOm) ..................................................................................................... 201
6.3.12 Timer output level register m (TOLm) ........................................................................................... 202
6.3.13 Timer output mode register m (TOMm) ........................................................................................ 203
6.3.14 Input switch control register (ISC) ................................................................................................ 204
6.3.15 Noise filter enable register 1 (NFEN1) .......................................................................................... 205
6.3.16 Port mode registers 1, 3 to 5, 14 (PM1, PM3 to PM5, PM14) ....................................................... 207
6.4 Basic Rules of Timer Array Unit ............................................................................................... 209
6.4.1 Basic rules of simultaneous channel operation function ................................................................. 209
6.4.2 Basic rules of 8-bit timer operation function (channels 1 and 3 only) ............................................. 211
6.5 Operation of Counter ................................................................................................................. 212
6.5.1 Count clock (fTCLK) .......................................................................................................................... 212
6.5.2 Start timing of counter .................................................................................................................... 214