Datasheet

RL78/G14 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105 C)
R01DS0053EJ0200 Rev. 2.00 Page 165 of 187
Oct 25, 2013
3.6.4 Comparator
Note Not usable in sub-clock operation or STOP mode.
3.6.5 POR circuit characteristics
Note 1. However, when the operating voltage falls while the LVD is off, enter STOP mode, or enable the reset status using the
external reset pin before the voltage falls below the operating voltage range shown in 3.4 AC Characteristics.
Note 2. Minimum time required for a POR reset when VDD exceeds below VPDR. This is also the minimum time required for a
POR reset from when V
DD exceeds below 0.7 V to when VDD exceeds VPOR while STOP mode is entered or the main
system clock is stopped through setting bit 0 (HIOSTOP) and bit 7 (MSTOP) in the clock operation status control register
(CSC).
(TA = -40 to +105 C, 2.4 V  EVDD0 = EVDD1  VDD  5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Input voltage range Ivref 0EV
DD0 - 1.4 V
Ivcmp -0.3 EV
DD0 + 0.3 V
Output delay td V
DD = 3.0 V
Input slew rate > 50 mV/
s
Comparator high-speed mode,
standard mode
1.2
s
Comparator high-speed mode,
window mode
2.0
s
Comparator low-speed mode,
standard mode
3.0 5.0
s
High-electric-potential
reference voltage
VTW+ Comparator high-speed mode, window mode 0.76 V
DD V
Low-electric-potential
reference voltage
VTW- Comparator high-speed mode, window mode 0.24 V
DD V
Operation stabilization
wait time
t
CMP 100 s
Internal reference voltage
Note
VBGR
2.4 V  VDD  5.5 V, HS (high-speed main) mode
1.38 1.45 1.50 V
(TA = -40 to +105 C, VSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Detection voltage V
POR Power supply rise time 1.45 1.51 1.57 V
V
PDR
Power supply fall time
Note 1
1.44 1.50 1.56 V
Minimum pulse width
Note 2
TPW
300 s
TPW
VPOR
VPDR or 0.7 V
Supply voltage (V
DD)