Datasheet

RL78/G14 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85 C)
R01DS0053EJ0200 Rev. 2.00 Page 99 of 187
Oct 25, 2013
Note 1. The first clock pulse is generated after this period when the start/restart condition is detected.
Note 2. The maximum value (MAX.) of tHD: DAT is during normal transfer and a wait state is inserted in the ACK (acknowledge)
timing.
Caution The values in the above table are applied even when bit 2 (PIOR02) in the peripheral I/O redirection register 0
(PIOR0) is 1. At this time, the pin characteristics (I
OH1, IOL1, VOH1, VOL1) must satisfy the values in the redirect
destination.
Remark
The maximum value of Cb (communication line capacitance) and the value of Rb (communication line pull-up resistor) at
that time in each mode are as follows.
Standard mode: C
b = 400 pF, Rb = 2.7 k
(1) I
2
C standard mode
(TA = -40 to +85 C, 1.6 V  EVDD0 = EVDD1  VDD  5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (2/2)
Parameter Symbol Conditions HS (high-speed main)
mode
LS (low-speed main)
mode
LV (low-voltage main)
mode
Unit
MIN. MAX. MIN. MAX. MIN. MAX.
Data setup time (reception) t
SU: DAT 2.7 V  EVDD0  5.5 V 250 250 250 ns
1.8 V
 EVDD0  5.5 V 250 250 250 ns
1.7 V
 EVDD0  5.5 V 250 250 250 ns
1.6 V
 EVDD0  5.5 V — 250 250 ns
Data hold time (transmission)
Note 2
tHD: DAT 2.7 V  EVDD0  5.5 V 0 3.45 0 3.45 0 3.45 s
1.8 V
 EVDD0  5.5 V 0 3.45 0 3.45 0 3.45 s
1.7 V
 EVDD0  5.5 V 0 3.45 0 3.45 0 3.45 s
1.6 V
 EVDD0  5.5 V — 03.4503.45s
Setup time of stop condition t
SU: STO 2.7 V  EVDD0  5.5 V 4.0 4.0 4.0 s
1.8 V
 EVDD0  5.5 V 4.0 4.0 4.0 s
1.7 V
 EVDD0  5.5 V 4.0 4.0 4.0 s
1.6 V
 EVDD0  5.5 V — 4.0 4.0 s
Bus-free time t
BUF 2.7 V  EVDD0  5.5 V 4.7 4.7 4.7 s
1.8 V
 EVDD0  5.5 V 4.7 4.7 4.7 s
1.7 V
 EVDD0  5.5 V 4.7 4.7 4.7 s
1.6 V
 EVDD0  5.5 V — 4.7 4.7 s