Datasheet

RL78/G14 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85 C)
R01DS0053EJ0200 Rev. 2.00 Page 87 of 187
Oct 25, 2013
Note Use it with EVDD0  Vb.
Caution Select the TTL input buffer for the SIp pin and the N-ch open drain output (VDD tolerance (When 30- to 52-pin
products)/EV
DD tolerance (When 64- to 100-pin products)) mode for the SOp pin and SCKp pin by using port
input mode register g (PIMg) and port output mode register g (POMg). For V
IH and VIL, see the DC characteristics
with TTL input buffer selected.
(Remarks are listed two pages after the next page.)
(8) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (master mode, SCKp... internal clock
output)
(T
A = -40 to +85 C, 1.8 V  EVDD0 = EVDD1  VDD  5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter Symbol Conditions HS (high-speed
main) mode
LS (low-speed main)
mode
LV (low-voltage
main) mode
Unit
MIN. MAX. MIN. MAX. MIN. MAX.
SCKp cycle time t
KCY1 tKCY1  4/fCLK 4.0 V  EVDD0  5.5 V,
2.7 V
 Vb  4.0 V,
C
b = 30 pF, Rb = 1.4 k
300 1150 1150 ns
2.7 V
 EVDD0 < 4.0 V,
2.3 V
 Vb  2.7 V,
C
b = 30 pF, Rb = 2.7 k
500 1150 1150 ns
1.8 V
 EVDD0 < 3.3 V,
1.6 V
 Vb  2.0 V
Note
,
C
b = 30 pF, Rb = 5.5 k
1150 1150 1150 ns
SCKp high-level
width
t
KH1 4.0 V  EVDD0  5.5 V,
2.7 V
 Vb  4.0 V,
C
b = 30 pF, Rb = 1.4 k
tKCY1/2 - 75 tKCY1/2 - 75 tKCY1/2 - 75 ns
2.7 V
 EVDD0 < 4.0 V,
2.3 V
 Vb  2.7 V,
C
b = 30 pF, Rb = 2.7 k
tKCY1/2 - 170 tKCY1/2 - 170 tKCY1/2 - 170 ns
1.8 V
 EVDD0 < 3.3 V,
1.6 V
 Vb  2.0 V
Note
,
C
b = 30 pF, Rb = 5.5 k
tKCY1/2 - 458 tKCY1/2 - 458 tKCY1/2 - 458 ns
SCKp low-level
width
t
KL1 4.0 V  EVDD0  5.5 V,
2.7 V
 Vb  4.0 V,
C
b = 30 pF, Rb = 1.4 k
tKCY1/2 - 12 tKCY1/2 - 50 tKCY1/2 - 50 ns
2.7 V
 EVDD0 < 4.0 V,
2.3 V
 Vb  2.7 V,
C
b = 30 pF, Rb = 2.7 k
tKCY1/2 - 18 tKCY1/2 - 50 tKCY1/2 - 50 ns
1.8 V
 EVDD0 < 3.3 V,
1.6 V
 Vb  2.0 V
Note
,
C
b = 30 pF, Rb = 5.5 k
tKCY1/2 - 50 tKCY1/2 - 50 tKCY1/2 - 50 ns
(1/3)