Datasheet

RL78/G14 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85 C)
R01DS0053EJ0200 Rev. 2.00 Page 85 of 187
Oct 25, 2013
(Notes, Caution, and Remarks are listed on the next page.)
(7) Communication at different potential (2.5 V, 3 V) (CSI mode) (master mode, SCKp... internal clock output,
corresponding CSI00 only)
(T
A = -40 to +85 C, 2.7 V  EVDD0 = EVDD1  VDD  5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter Symbol Conditions HS (high-speed
main) mode
LS (low-speed main)
mode
LV (low-voltage
main) mode
Unit
MIN. MAX. MIN. MAX. MIN. MAX.
SCKp cycle time t
KCY1 tKCY1  2/fCLK
4.0 V  EVDD0  5.5 V,
2.7 V
 Vb  4.0 V,
C
b = 20 pF, Rb = 1.4 k
200 1150 1150 ns
2.7 V
 EVDD0  4.0 V,
2.3 V
 Vb  2.7 V,
C
b = 20 pF, Rb = 2.7 k
300 1150 1150 ns
SCKp high-level
width
t
KH1
4.0 V  EVDD0  5.5 V,
2.7 V
 Vb  4.0 V,
C
b = 20 pF, Rb = 1.4 k
tKCY1/2 - 50 tKCY1/2 - 50 tKCY1/2 - 50 ns
2.7 V
 EVDD0  4.0 V,
2.3 V
 Vb  2.7 V,
C
b = 20 pF, Rb = 2.7 k
tKCY1/2 - 120 tKCY1/2 - 120 tKCY1/2 - 120 ns
SCKp low-level
width
t
KL1
4.0 V  EVDD0  5.5 V,
2.7 V
 Vb  4.0 V,
C
b = 20 pF, Rb = 1.4 k
tKCY1/2 - 7 tKCY1/2 - 50 tKCY1/2 - 50 ns
2.7 V
 EVDD0  4.0 V,
2.3 V
 Vb  2.7 V,
C
b = 20 pF, Rb = 2.7 k
tKCY1/2 - 10 tKCY1/2 - 50 tKCY1/2 - 50 ns
SIp setup time
(to SCKp↑)
Note 1
tSIK1
4.0 V  EVDD0  5.5 V,
2.7 V
 Vb  4.0 V,
C
b = 20 pF, Rb = 1.4 k
58 479 479 ns
2.7 V
 EVDD0  4.0 V,
2.3 V
 Vb  2.7 V,
C
b = 20 pF, Rb = 2.7 k
121 479 479 ns
SIp hold time
(from SCKp↑)
Note 1
tKSI1
4.0 V  EVDD0  5.5 V,
2.7 V
 Vb  4.0 V,
C
b = 20 pF, Rb = 1.4 k
10 10 10 ns
2.7 V
 EVDD0  4.0 V,
2.3 V
 Vb  2.7 V,
C
b = 20 pF, Rb = 2.7 k
10 10 10 ns
Delay time from
SCKp
to SOp
output
Note 1
tKSO1
4.0 V  EVDD0  5.5 V,
2.7 V
 Vb  4.0 V,
C
b = 20 pF, Rb = 1.4 k
60 60 60 ns
2.7 V
 EVDD0  4.0 V,
2.3 V
 Vb  2.7 V,
C
b = 20 pF, Rb = 2.7 k
130 130 130 ns
(1/2)