Datasheet

RL78/G14 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85 C)
R01DS0053EJ0200 Rev. 2.00 Page 79 of 187
Oct 25, 2013
Note 1. The value must also be equal to or less than fMCK/4.
Note 2. Set the fMCK value to keep the hold time of SCLr = “L” and SCLr = “H”.
Caution Select the normal input buffer and the N-ch open drain output (VDD tolerance (When 30- to 52-pin products)/EVDD
tolerance (When 64- to 100-pin products)) mode for the SDAr pin and the normal output mode for the SCLr pin by
using port input mode register g (PIMg) and port output mode register h (POMh).
(Remarks are listed on the next page.)
(5) During communication at same potential (simplified I
2
C mode)
(TA = -40 to +85 C, 1.6 V  EVDD0 = EVDD1  VDD  5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (2/2)
Parameter Symbol Conditions HS (high-speed main)
mode
LS (low-speed main)
mode
LV (low-voltage main)
mode
Unit
MIN. MAX. MIN. MAX. MIN. MAX.
Data setup time
(reception)
t
SU: DAT
2.7 V  EVDD0  5.5 V,
C
b = 50 pF, Rb = 2.7 k
1/fMCK + 85
Note 2
1/fMCK + 145
Note 2
1/fMCK + 145
Note 2
ns
1.8 V
 EVDD0  5.5 V,
C
b = 100 pF, Rb = 3 k
1/fMCK + 145
Note 2
1/fMCK + 145
Note 2
1/fMCK + 145
Note 2
ns
1.8 V
 EVDD0  2.7 V,
C
b = 100 pF, Rb = 5 k
1/fMCK + 230
Note 2
1/fMCK + 230
Note 2
1/fMCK + 230
Note 2
ns
1.7 V
 EVDD0  1.8 V,
C
b = 100 pF, Rb = 5 k
1/fMCK + 290
Note 2
1/fMCK + 290
Note 2
1/fMCK + 290
Note 2
ns
1.6 V
 EVDD0  1.8 V,
C
b = 100 pF, Rb = 5 k
—
1/f
MCK + 290
Note 2
1/fMCK + 290
Note 2
ns
Data hold time
(transmission)
t
HD: DAT
2.7 V  EVDD0  5.5 V,
C
b = 50 pF, Rb = 2.7 k
030503050305ns
1.8 V
 EVDD0  5.5 V,
C
b = 100 pF, Rb = 3 k
035503550355ns
1.8 V
 EVDD0  2.7 V,
C
b = 100 pF, Rb = 5 k
040504050405ns
1.7 V
 EVDD0  1.8 V,
C
b = 100 pF, Rb = 5 k
040504050405ns
1.6 V
 EVDD0  1.8 V,
C
b = 100 pF, Rb = 5 k
— 0 405 0 405 ns