Datasheet

RL78/G14 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85 C)
R01DS0053EJ0200 Rev. 2.00 Page 74 of 187
Oct 25, 2013
Note 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to SCKp↓” when
DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
Note 2. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from SCKp↓” when
DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
Note 3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes “from
SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
Note 4. C is the load capacitance of the SOp output lines.
Note 5. The maximum transfer rate when using the SNOOZE mode is 1 Mbps.
Caution Select the normal input buffer for the SIp pin and SCKp pin and the normal output mode for the SOp pin by using
port input mode register g (PIMg) and port output mode register g (POMg).
(4) During communication at same potential (CSI mode) (slave mode, SCKp... external clock input)
(T
A = -40 to +85 C, 1.6 V  EVDD0 = EVDD1  VDD  5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter Symbol Conditions HS (high-speed main)
mode
LS (low-speed main)
mode
LV (low-voltage main)
mode
Unit
MIN. MAX. MIN. MAX. MIN. MAX.
SCKp cycle
time
Note 5
tKCY2
4.0 V  EVDD0  5.5 V
20 MHz  f
MCK 8/fMCK ——ns
f
MCK  20 MHz
6/f
MCK 6/fMCK 6/fMCK ns
2.7 V  EVDD0  5.5 V
16 MHz  f
MCK 8/fMCK ——ns
f
MCK  16 MHz
6/f
MCK 6/fMCK 6/fMCK ns
2.4 V  EVDD0  5.5 V
6/f
MCK
and 500
6/f
MCK
and 500
6/f
MCK
and 500
ns
1.8 V
 EVDD0  5.5 V
6/f
MCK
and 750
6/f
MCK
and 750
6/f
MCK
and 750
ns
1.7 V
 EVDD0  5.5 V
6/f
MCK
and 1500
6/f
MCK
and 1500
6/f
MCK
and 1500
ns
1.6 V
 EVDD0  5.5 V
—6/f
MCK
and 1500
6/f
MCK
and 1500
ns
SCKp high-/
low-level width
t
KH2,
t
KL2
4.0 V  EVDD0  5.5 V
t
KCY2/2 - 7 tKCY2/2 - 7 tKCY2/2 - 7 ns
2.7 V
 EVDD0  5.5 V
t
KCY2/2 - 8 tKCY2/2 - 8 tKCY2/2 - 8 ns
1.8 V  EVDD0  5.5 V
t
KCY2/2 - 18 tKCY2/2 - 18 tKCY2/2 - 18 ns
1.7 V  EVDD0  5.5 V
t
KCY2/2 - 66 tKCY2/2 - 66 tKCY2/2 - 66 ns
1.6 V  EVDD0  5.5 V
—t
KCY2/2 - 66 tKCY2/2 - 66 ns
SIp setup time
(to SCKp↑)
Note 1
tSIK2
2.7 V  EVDD0  5.5 V
1/f
MCK + 20 1/fMCK + 30 1/fMCK + 30 ns
1.8 V  EVDD0  5.5 V
1/f
MCK + 30 1/fMCK + 30 1/fMCK + 30 ns
1.7 V  EVDD0  5.5 V
1/f
MCK + 40 1/fMCK + 40 1/fMCK + 40 ns
1.6 V  EVDD0  5.5 V
—1/f
MCK + 40 1/fMCK + 40 ns
SIp hold time
(from SCKp↑)
Note 2
tKSI2
1.8 V  EVDD0  5.5 V
1/f
MCK + 31 1/fMCK + 31 1/fMCK + 31 ns
1.7 V  EVDD0  5.5 V
1/f
MCK + 250 1/fMCK + 250 1/fMCK + 250 ns
1.6 V  EVDD0  5.5 V
—1/f
MCK + 250 1/fMCK + 250 ns
Delay time
from SCKp↓ to
SOp output
Note 3
tKSO2
C = 30 pF
Note 4
2.7 V  EVDD0  5.5 V
2/f
MCK
+ 44
2/fMCK
+ 110
2/fMCK
+ 110
ns
2.4 V
 EVDD0  5.5 V
2/f
MCK
+ 75
2/fMCK
+ 110
2/fMCK
+ 110
ns
1.8 V
 EVDD0  5.5 V
2/f
MCK
+ 100
2/fMCK
+ 110
2/fMCK
+ 110
ns
1.7 V
 EVDD0  5.5 V
2/f
MCK
+ 220
2/fMCK
+ 220
2/fMCK
+ 220
ns
1.6 V
 EVDD0  5.5 V
—2/f
MCK
+ 220
2/fMCK
+ 220
ns
(1/2)