Datasheet

RL78/G14 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85 C)
R01DS0053EJ0200 Rev. 2.00 Page 73 of 187
Oct 25, 2013
Note 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to SCKp↓” when
DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
Note 2. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from SCKp↓” when
DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
Note 3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes “from
SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
Note 4. C is the load capacitance of the SCKp and SOp output lines.
Caution Select the normal input buffer for the SIp pin and the normal output mode for the SOp pin and SCKp pin by using
port input mode register g (PIMg) and port output mode register g (POMg).
Remark 1.
p: CSI number (p = 00, 01, 10, 11, 20, 21, 30, 31), m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3),
g: PIM number (g = 0, 1, 3 to 5, 14)
Remark 2. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number,
n: Channel number (mn = 00 to 03, 10 to 13))
(3) During communication at same potential (CSI mode) (master mode, SCKp... internal clock output)
(T
A = -40 to +85 C, 1.6 V  EVDD0 = EVDD1  VDD  5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter Symbol Conditions HS (high-speed
main) mode
LS (low-speed main)
mode
LV (low-voltage
main) mode
Unit
MIN. MAX. MIN. MAX. MIN. MAX.
SCKp cycle time t
KCY1
tKCY1  4/fCLK 2.7 V  EVDD0  5.5 V
125 500 1000 ns
2.4 V
 EVDD0  5.5 V
250 500 1000 ns
1.8 V
 EVDD0  5.5 V
500 500 1000 ns
1.7 V
 EVDD0  5.5 V
1000 1000 1000 ns
1.6 V
 EVDD0  5.5 V
— 1000 1000 ns
SCKp high-/low-level
width
t
KH1,
t
KL1
4.0 V  EVDD0  5.5 V
t
KCY1/2 - 12 tKCY1/2 - 50 tKCY1/2 - 50 ns
2.7 V  EVDD0  5.5 V
t
KCY1/2 - 18 tKCY1/2 - 50 tKCY1/2 - 50 ns
2.4 V  EVDD0  5.5 V
t
KCY1/2 - 38 tKCY1/2 - 50 tKCY1/2 - 50 ns
1.8 V  EVDD0  5.5 V
t
KCY1/2 - 50 tKCY1/2 - 50 tKCY1/2 - 50 ns
1.7 V  EVDD0  5.5 V
t
KCY1/2 - 100 tKCY1/2 - 100 tKCY1/2 - 100 ns
1.6 V  EVDD0  5.5 V
—t
KCY1/2 - 100 tKCY1/2 - 100 ns
SIp setup time
(to SCKp↑)
Note 1
tSIK1
4.0 V  EVDD0  5.5 V
44 110 110 ns
2.7 V
 EVDD0  5.5 V
44 110 110 ns
2.4 V
 EVDD0  5.5 V
75 110 110 ns
1.8 V
 EVDD0  5.5 V
110 110 110 ns
1.7 V
 EVDD0  5.5 V
220 220 220 ns
1.6 V
 EVDD0  5.5 V
—220220ns
SIp hold time
(from SCKp↑)
Note 2
tKSI1
1.7 V  EVDD0  5.5 V
19 19 19 ns
1.6 V
 EVDD0  5.5 V
—1919ns
Delay time from
SCKp↓ to SOp output
Note 3
tKSO1
1.7 V  EVDD0  5.5 V
C = 30 pF
Note 4
25 25 25 ns
1.6 V
 EVDD0  5.5 V
C = 30 pF
Note 4
—2525ns