Datasheet

RL78/G14 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85 C)
R01DS0053EJ0200 Rev. 2.00 Page 63 of 187
Oct 25, 2013
2.4 AC Characteristics
Note The following conditions are required for low voltage interface when EVDD0 < VDD
1.8 V  EVDD0 < 2.7 V: MIN. 125 ns
1.6 V  EV
DD0 < 1.8 V: MIN. 250 ns
Remark fMCK: Timer array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of timer mode register mn (TMRmn). m: Unit number (m = 0, 1), n: Channel
number (n = 0 to 3))
(TA = -40 to +85 C, 1.6 V  EVDD0 = EVDD1  VDD  5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Items Symbol Conditions MIN. TYP. MAX. Unit
Instruction cycle
(minimum instruction
execution time)
T
CY Main system
clock (f
MAIN)
operation
HS (high-speed main)
mode
2.7 V  V
DD  5.5 V 0.03125 1 s
2.4 V  V
DD < 2.7 V 0.0625 1 s
LS (low-speed main)
mode
1.8 V  V
DD  5.5 V 0.125 1 s
LV (low-voltage main)
mode
1.6 V  V
DD  5.5 V 0.25 1 s
Subsystem clock (f
SUB) operation 1.8 V  VDD  5.5 V 28.5 30.5 31.3 s
In the self-
programming
mode
HS (high-speed main)
mode
2.7 V  V
DD  5.5 V 0.03125 1 s
2.4 V  V
DD < 2.7 V 0.0625 1 s
LS (low-speed main)
mode
1.8 V  V
DD  5.5 V 0.125 1 s
LV (low-voltage main)
mode
1.8 V  V
DD  5.5 V 0.25 1 s
External system clock
frequency
f
EX 2.7 V  VDD  5.5 V 1.0 20.0 MHz
2.4 V  V
DD  2.7 V 1.0 16.0 MHz
1.8 V  V
DD < 2.4 V 1.0 8.0 MHz
1.6 V  V
DD < 1.8 V 1.0 4.0 MHz
f
EXS 32 35 kHz
External system clock
input high-level width,
low-level width
t
EXH,
t
EXL
2.7 V  VDD  5.5 V 24 ns
2.4 V  V
DD  2.7 V 30 ns
1.8 V  V
DD < 2.4 V 60 ns
1.6 V  V
DD < 1.8 V 120 ns
t
EXHS,
t
EXLS
13.7 s
TI00 to TI03, TI10 to
TI13 input high-level
width, low-level width
t
TIH, tTIL 1/fMCK + 10
Note
ns
Timer RJ input cycle f
C TRJIO 2.7 V  EVDD0  5.5 V 100 ns
1.8 V  EV
DD0 < 2.7 V 300 ns
1.6 V  EV
DD0 < 1.8 V 500 ns
Timer RJ input high-
level width, low-level
width
t
TJIH,
t
TJIL
TRJIO 2.7 V  EVDD0  5.5 V 40 ns
1.8 V  EV
DD0 < 2.7 V 120 ns
1.6 V  EV
DD0 < 1.8 V 200 ns
(1/2)