Datasheet

RL78/G14 1. OUTLINE
R01DS0053EJ0200 Rev. 2.00 Page 43 of 187
Oct 25, 2013
(2/2)
Note The illegal instruction is generated when instruction code FFH is executed.
Reset by the illegal instruction execution is not issued by emulation with the in-circuit emulator or on-chip debug
emulator.
Item
80-pin 100-pin
R5F104Mx
(x = F to H, J)
R5F104Px
(x = F to H, J)
Clock output/buzzer output 2 2
• 2.44 kHz, 4.88 kHz, 9.76 kHz, 1.25 MHz, 2.5 MHz, 5 MHz, 10 MHz
(Main system clock: f
MAIN = 20 MHz operation)
• 256 Hz, 512 Hz, 1.024 kHz, 2.048 kHz, 4.096 kHz, 8.192 kHz, 16.384 kHz, 32.768 kHz
(Subsystem clock: f
SUB = 32.768 kHz operation)
8/10-bit resolution A/D converter 17 channels 20 channels
D/A converter 2 channels 2 channels
Comparator 2 channels 2 channels
Serial interface [80-pin, 100-pin products]
• CSI: 2 channels/UART (UART supporting LIN-bus): 1 channel/simplified I
2
C: 2 channels
• CSI: 2 channels/UART: 1 channel/simplified I
2
C: 2 channels
• CSI: 2 channels/UART: 1 channel/simplified I
2
C: 2 channels
• CSI: 2 channels/UART: 1 channel/simplified I
2
C: 2 channels
I
2
C bus
2 channels 2 channels
Data transfer controller (DTC) 39 sources 39 sources
Event link controller (ELC) Event input: 26
Event trigger output: 9
Vectored
interrupt sources
Internal 32 32
External 13 13
Key interrupt 8 8
Reset
• Reset by RESET
pin
• Internal reset by watchdog timer
• Internal reset by power-on-reset
• Internal reset by voltage detector
• Internal reset by illegal instruction execution
Note
• Internal reset by RAM parity error
• Internal reset by illegal-memory access
Power-on-reset circuit • Power-on-reset: 1.51 ±0.03 V
• Power-down-reset: 1.50 ±0.03 V
Voltage detector 1.63 V to 4.06 V (14 stages)
On-chip debug function Provided
Power supply voltage V
DD = 1.6 to 5.5 V
Operating ambient temperature T
A = 40 to +85 °C