Datasheet

RL78/G14 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105 C)
R01DS0053EJ0200 Rev. 2.00 Page 157 of 187
Oct 25, 2013
Note 1. The value must also be equal to or less than fMCK/4.
Note 2. Set the fMCK value to keep the hold time of SCLr = “L” and SCLr = “H”.
Caution Select the TTL input buffer and the N-ch open drain output (VDD tolerance (When 30- to 52-pin products)/EVDD
tolerance (When 64- to 100-pin products)) mode for the SDAr pin and the N-ch open drain output (VDD tolerance
(When 30- to 52-pin products)/EV
DD tolerance (When 64- to 100-pin products)) mode for the SCLr pin by using
port input mode register g (PIMg) and port output mode register g (POMg). For V
IH and VIL, see the DC
characteristics with TTL input buffer selected.
(Remarks are listed on the next page.)
(8) Communication at different potential (1.8 V, 2.5 V, 3 V) (simplified I
2
C mode)
(TA = -40 to +105 C, 2.4 V  EVDD0 = EVDD1  VDD  5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (2/2)
Parameter Symbol Conditions HS (high-speed main) mode Unit
MIN. MAX.
Data setup time (reception) t
SU:DAT 4.0 V  EVDD0  5.5 V,
2.7 V
 Vb  4.0 V,
C
b = 50 pF, Rb = 2.7 k
1/fMCK + 340
Note 2
ns
2.7 V
 EVDD0 < 4.0 V,
2.3 V
 Vb  2.7 V,
C
b = 50 pF, Rb = 2.7 k
1/fMCK + 340
Note 2
ns
4.0 V
 EVDD0  5.5 V,
2.7 V
 Vb  4.0 V,
C
b = 100 pF, Rb = 2.8 k
1/fMCK + 760
Note 2
ns
2.7 V
 EVDD0 < 4.0 V,
2.3 V
 Vb  2.7 V,
C
b = 100 pF, Rb = 2.7 k
1/fMCK + 760
Note 2
ns
2.4 V
 EVDD0 < 3.3 V,
1.6 V
 Vb  2.0 V,
C
b = 100 pF, Rb = 5.5 k
1/fMCK + 570
Note 2
ns
Data hold time (transmission) t
HD:DAT 4.0 V  EVDD0  5.5 V,
2.7 V
 Vb  4.0 V,
C
b = 50 pF, Rb = 2.7 k
0 770 ns
2.7 V
 EVDD0 < 4.0 V,
2.3 V
 Vb  2.7 V,
C
b = 50 pF, Rb = 2.7 k
0 770 ns
4.0 V
 EVDD0  5.5 V,
2.7 V
 Vb  4.0 V,
C
b = 100 pF, Rb = 2.8 k
0 1420 ns
2.7 V
 EVDD0 < 4.0 V,
2.3 V
 Vb  2.7 V,
C
b = 100 pF, Rb = 2.7 k
0 1420 ns
2.4 V
 EVDD0 < 3.3 V,
1.6 V
 Vb  2.0 V,
C
b = 100 pF, Rb = 5.5 k
0 1215 ns