Datasheet

RL78/G14 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105 C)
R01DS0053EJ0200 Rev. 2.00 Page 153 of 187
Oct 25, 2013
(Notes, Cautions, and Remarks are listed on the next page.)
(7) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (slave mode, SCKp... external clock
input)
(T
A = -40 to +105 C, 2.4 V  EVDD0 = EVDD1  VDD  5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter Symbol Conditions HS (high-speed main) mode Unit
MIN. MAX.
SCKp cycle time
Note 1
tKCY2 4.0 V  EVDD0  5.5 V,
2.7 V
 Vb  4.0 V
24 MHz
 fMCK 28/fMCK ns
20 MHz
 fMCK  24 MHz 24/fMCK ns
8 MHz
 fMCK  20 MHz 20/fMCK ns
4 MHz
 fMCK  8 MHz 16/fMCK ns
f
MCK  4 MHz 12/fMCK ns
2.7 V
 EVDD0  4.0 V,
2.3 V
 Vb  2.7 V
24 MHz
 fMCK 40/fMCK ns
20 MHz
 fMCK  24 MHz 32/fMCK ns
16 MHz
 fMCK  20 MHz 28/fMCK ns
8 MHz
 fMCK  16 MHz 24/fMCK ns
4 MHz
 fMCK  8 MHz 16/fMCK ns
f
MCK  4 MHz 12/fMCK ns
2.4 V
 EVDD0  3.3 V,
1.6 V
 Vb  2.0 V
24 MHz
 fMCK 96/fMCK ns
20 MHz
 fMCK  24 MHz 72/fMCK ns
16 MHz
 fMCK  20 MHz 64/fMCK ns
8 MHz
 fMCK  16 MHz 52/fMCK ns
4 MHz
 fMCK  8 MHz 32/fMCK ns
f
MCK  4 MHz 20/fMCK ns
SCKp high-/low-level
width
t
KH2, tKL2 4.0 V  EVDD0  5.5 V, 2.7 V  Vb  4.0 V tKCY2/2 - 24 ns
2.7 V
 EVDD0  4.0 V, 2.3 V  Vb  2.7 V tKCY2/2 - 36 ns
2.4 V
 EVDD0  3.3 V, 1.6 V  Vb  2.0 V tKCY2/2 - 100 ns
SIp setup time
(to SCKp
↑)
Note 2
tSIK2 4.0 V  EVDD0  5.5 V, 2.7 V  Vb  4.0 V 1/fMCK + 40 ns
2.7 V
 EVDD0  4.0 V, 2.3 V  Vb  2.7 V 1/fMCK + 40 ns
2.4 V
 EVDD0  3.3 V, 1.6 V  Vb  2.0 V 1/fMCK + 60 ns
SIp hold time
(from SCKp
↑)
Note 3
tKSI2 1/fMCK + 62 ns
Delay time from SCKp

to SOp output
Note 4
tKSO2 4.0 V  EVDD0  5.5 V, 2.7 V  Vb  4.0 V,
C
b = 30 pF, Rb = 1.4 k
2/fMCK + 240 ns
2.7 V
 EVDD0  4.0 V, 2.3 V  Vb  2.7 V,
C
b = 30 pF, Rb = 2.7 k
2/fMCK + 428 ns
2.4 V
 EVDD0  3.3 V, 1.6 V  Vb  2.0 V,
C
b = 30 pF, Rv = 5.5 k
2/fMCK + 1146 ns