Datasheet

RL78/G14 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105 C)
R01DS0053EJ0200 Rev. 2.00 Page 149 of 187
Oct 25, 2013
Note When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.
Caution Select the TTL input buffer for the SIp pin and the N-ch open drain output (VDD tolerance (When 30- to 52-pin
products)/EV
DD tolerance (When 64- to 100-pin products)) mode for the SOp pin and SCKp pin by using port
input mode register g (PIMg) and port output mode register g (POMg). For V
IH and VIL, see the DC characteristics
with TTL input buffer selected.
(Remarks are listed on the page after the next page.)
(6) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (master mode, SCKp... internal clock
output)
(T
A = -40 to +105 C, 2.4 V  EVDD0 = EVDD1  VDD  5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (2/3)
Parameter Symbol Conditions HS (high-speed main) mode Unit
MIN. MAX.
SIp setup time (to SCKp↑)
Note
tSIK1 4.0 V  EVDD0  5.5 V,
2.7 V
 Vb  4.0 V,
C
b = 30 pF, Rb = 1.4 k
162 ns
2.7 V
 EVDD0 < 4.0 V,
2.3 V
 Vb  2.7 V,
C
b = 30 pF, Rb = 2.7 k
354 ns
2.4 V
 EVDD0 < 3.3 V,
1.6 V
 Vb  2.0 V,
C
b = 30 pF, Rb = 5.5 k
958 ns
SIp hold time (from SCKp↑)
Note
tKSI1 4.0 V  EVDD0  5.5 V,
2.7 V
 Vb  4.0 V,
C
b = 30 pF, Rb = 1.4 k
38 ns
2.7 V
 EVDD0 < 4.0 V,
2.3 V
 Vb  2.7 V,
C
b = 30 pF, Rb = 2.7 k
38 ns
2.4 V
 EVDD0 < 3.3 V,
1.6 V
 Vb  2.0 V,
C
b = 30 pF, Rb = 5.5 k
38 ns
Delay time from SCKp↓ to SOp output
Note
tKSO1 4.0 V  EVDD0  5.5 V,
2.7 V
 Vb  4.0 V,
C
b = 30 pF, Rb = 1.4 k
200 ns
2.7 V
 EVDD0 < 4.0 V,
2.3 V
 Vb  2.7 V,
C
b = 30 pF, Rb = 2.7 k
390 ns
2.4 V
 EVDD0 < 3.3 V,
1.6 V
 Vb  2.0 V,
C
b = 30 pF, Rb = 5.5 k
966 ns