Datasheet

RL78/G14 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105 C)
R01DS0053EJ0200 Rev. 2.00 Page 148 of 187
Oct 25, 2013
Caution Select the TTL input buffer for the SIp pin and the N-ch open drain output (VDD tolerance (When 30- to 52-pin
products)/EV
DD tolerance (When 64- to 100-pin products)) mode for the SOp pin and SCKp pin by using port
input mode register g (PIMg) and port output mode register g (POMg). For V
IH and VIL, see the DC characteristics
with TTL input buffer selected.
(Remarks are listed two pages after the next page.)
(6) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (master mode, SCKp... internal clock
output)
(T
A = -40 to +105 C, 2.4 V  EVDD0 = EVDD1  VDD  5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter Symbol Conditions HS (high-speed main) mode Unit
MIN. MAX.
SCKp cycle time t
KCY1 tKCY1  4/fCLK 4.0 V  EVDD0  5.5 V,
2.7 V
 Vb  4.0 V,
C
b = 30 pF, Rb = 1.4 k
600 ns
2.7 V
 EVDD0 < 4.0 V,
2.3 V
 Vb  2.7 V,
C
b = 30 pF, Rb = 2.7 k
1000 ns
2.4 V
 EVDD0 < 3.3 V,
1.6 V
 Vb  2.0 V,
C
b = 30 pF, Rb = 5.5 k
2300 ns
SCKp high-level width t
KH1 4.0 V  EVDD0  5.5 V,
2.7 V
 Vb  4.0 V,
C
b = 30 pF, Rb = 1.4 k
tKCY1/2 - 150 ns
2.7 V
 EVDD0 < 4.0 V,
2.3 V
 Vb  2.7 V,
C
b = 30 pF, Rb = 2.7 k
tKCY1/2 - 340 ns
2.4 V
 EVDD0 < 3.3 V,
1.6 V
 Vb  2.0 V,
C
b = 30 pF, Rb = 5.5 k
tKCY1/2 - 916 ns
SCKp low-level width t
KL1 4.0 V  EVDD0  5.5 V,
2.7 V
 Vb  4.0 V,
C
b = 30 pF, Rb = 1.4 k
tKCY1/2 - 24 ns
2.7 V
 EVDD0 < 4.0 V,
2.3 V
 Vb  2.7 V,
C
b = 30 pF, Rb = 2.7 k
tKCY1/2 - 36 ns
2.4 V
 EVDD0 < 3.3 V,
1.6 V
 Vb  2.0 V,
C
b = 30 pF, Rb = 5.5 k
tKCY1/2 - 100 ns
(1/3)