Datasheet

RL78/G14 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105 C)
R01DS0053EJ0200 Rev. 2.00 Page 146 of 187
Oct 25, 2013
Note 5. The smaller maximum transfer rate derived by using fMCK/12 or the following expression is the valid maximum transfer
rate.
Expression for calculating the transfer rate when 2.4 V
 EVDD0 < 3.3 V and 1.6 V  Vb  2.0 V
Note 6. This value as an example is calculated when the conditions described in the “Conditions” column are met.
Refer to
Note 5 above to calculate the maximum transfer rate under conditions of the customer.
Caution Select the TTL input buffer for the RxDq pin and the N-ch open drain output (VDD tolerance (When 30- to 52-pin
products)/EV
DD tolerance (When 64- to 100-pin products)) mode for the TxDq pin by using port input mode
register g (PIMg) and port output mode register g (POMg). For V
IH and VIL, see the DC characteristics with TTL
input buffer selected.
(Remarks are listed on the next page.)
Maximum transfer rate =
1
[bps]
Baud rate error (theoretical value) =
1
Transfer rate  2
-
{-C
b  Rb  In (1 - )}  3
1.5
V
b
{-Cb  Rb  In (1 - )}
1.5
V
b
( )  Number of transferred bits
1
Transfer rate
 100 [%]
* This value is the theoretical value of the relative difference between the transmission and reception sides.