Datasheet

RL78/G14 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105 C)
R01DS0053EJ0200 Rev. 2.00 Page 144 of 187
Oct 25, 2013
Note 1. Transfer rate in the SNOOZE mode is 4800 bps only.
However, the SNOOZE mode cannot be used when FRQSEL4 = 1.
Note 2. The following conditions are required for low voltage interface when EVDD0 < VDD.
2.4 V
 EVDD0  2.7 V: MAX. 1.3 Mbps
Note 3. The maximum operating frequencies of the CPU/peripheral hardware clock (fCLK) are:
HS (high-speed main) mode: 32 MHz (2.7 V
 VDD  5.5 V)
16 MHz (2.4 V
 VDD  5.5 V)
Caution Select the TTL input buffer for the RxDq pin and the N-ch open drain output (VDD tolerance (When 30- to 52-pin
products)/EV
DD tolerance (When 64- to 100-pin products)) mode for the TxDq pin by using port input mode
register g (PIMg) and port output mode register g (POMg). For V
IH and VIL, see the DC characteristics with TTL
input buffer selected.
Remark 1.
Vb [V]: Communication line voltage
Remark 2. q: UART number (q = 0 to 3), g: PIM and POM number (g = 0, 1, 5, 14)
Remark 3. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number,
n: Channel number (mn = 00 to 03, 10 to 13)
Remark 4. UART2 cannot communicate at different potential when bit 1 (PIOR01) of peripheral I/O redirection register 0 (PIOR0) is
1.
(5) Communication at different potential (1.8 V, 2.5 V, 3 V) (UART mode)
(T
A = -40 to +105 C, 2.4 V  EVDD0 = EVDD1  VDD  5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter Symbol Conditions HS (high-speed main) mode Unit
MIN. MAX.
Transfer rate reception
4.0 V
 EVDD0  5.5 V,
2.7 V
 Vb  4.0 V
f
MCK/12
Note 1
bps
Theoretical value of the maximum transfer rate
f
MCK = fCLK
Note 3
2.6 Mbps
2.7 V
 EVDD0  4.0 V,
2.3 V
 Vb  2.7 V
f
MCK/12
Note 1
bps
Theoretical value of the maximum transfer rate
f
MCK = fCLK
Note 3
2.6 Mbps
2.4 V
 EVDD0  3.3 V,
1.6 V
 Vb  2.0 V
f
MCK/12
Notes 1, 2
bps
Theoretical value of the maximum transfer rate
f
MCK = fCLK
Note 3
2.6 Mbps
(1/2)