Datasheet

RL78/G14 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105 C)
R01DS0053EJ0200 Rev. 2.00 Page 142 of 187
Oct 25, 2013
Note 1. The value must also be equal to or less than fMCK/4.
Note 2. Set the fMCK value to keep the hold time of SCLr = “L” and SCLr = “H”.
Caution Select the normal input buffer and the N-ch open drain output (VDD tolerance (When 30- to 52-pin products)/EVDD
tolerance (When 64- to 100-pin products)) mode for the SDAr pin and the normal output mode for the SCLr pin by
using port input mode register g (PIMg) and port output mode register h (POMh).
(Remarks are listed on the next page.)
(4) During communication at same potential (simplified I
2
C mode)
(TA = -40 to +105 C, 2.4 V  EVDD0 = EVDD1  VDD  5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter Symbol Conditions HS (high-speed main) mode Unit
MIN. MAX.
SCLr clock frequency f
SCL
2.7 V  EVDD0  5.5 V,
C
b = 50 pF, Rb = 2.7 k
400
Note 1
kHz
2.4 V
 EVDD0  5.5 V,
C
b = 100 pF, Rb = 3 k
100
Note 1
kHz
Hold time when SCLr = “L” t
LOW
2.7 V  EVDD0  5.5 V,
C
b = 50 pF, Rb = 2.7 k
1200 ns
2.4V
 EVDD0  5.5 V,
C
b = 100 pF, Rb = 3 k
4600 ns
Hold time when SCLr = “H” t
HIGH
2.7 V  EVDD0  5.5 V,
C
b = 50 pF, Rb = 2.7 k
1200 ns
2.4 V
 EVDD0  5.5 V,
C
b = 100 pF, Rb = 3 k
4600 ns
Data setup time (reception) t
SU: DAT
2.7 V  EVDD0  5.5 V,
C
b = 50 pF, Rb = 2.7 k
1/fMCK + 220
Note 2
ns
2.4V
 EVDD0  5.5 V,
C
b = 100 pF, Rb = 3 k
1/fMCK + 580
Note 2
ns
Data hold time (transmission) t
HD: DAT
2.7 V  EVDD0  5.5 V,
C
b = 50 pF, Rb = 2.7 k
0 770 ns
2.4 V
 EVDD0  5.5 V,
C
b = 100 pF, Rb = 3 k
0 1420 ns