Datasheet

RL78/G14 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105 C)
R01DS0053EJ0200 Rev. 2.00 Page 138 of 187
Oct 25, 2013
Note 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to SCKp↓” when
DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
Note 2. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from SCKp↓” when
DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
Note 3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes “from
SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
Note 4. C is the load capacitance of the SCKp and SOp output lines.
Caution Select the normal input buffer for the SIp pin and the normal output mode for the SOp pin and SCKp pin by using
port input mode register g (PIMg) and port output mode register g (POMg).
Remark 1.
p: CSI number (p = 00, 01, 10, 11, 20, 21, 30, 31), m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3),
g: PIM number (g = 0, 1, 3 to 5, 14)
Remark 2. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number,
n: Channel number (mn = 00 to 03, 10 to 13))
(2) During communication at same potential (CSI mode) (master mode, SCKp... internal clock output)
(T
A = -40 to +105 C, 2.4 V  EVDD0 = EVDD1  VDD  5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter Symbol Conditions HS (high-speed main)
mode
Unit
MIN. MAX.
SCKp cycle time t
KCY1
tKCY1  4/fCLK 2.7 V  EVDD0  5.5 V
250 ns
2.4 V
 EVDD0  5.5 V
500 ns
SCKp high-/low-level width t
KH1, tKL1
4.0 V  EVDD0  5.5 V
t
KCY1/2 - 24 ns
2.7 V
 EVDD0  5.5 V
t
KCY1/2 - 36 ns
2.4 V
 EVDD0  5.5 V
t
KCY1/2 - 76 ns
SIp setup time (to SCKp↑)
Note 1
tSIK1
4.0 V  EVDD0  5.5 V
66 ns
2.7 V
 EVDD0  5.5 V
66 ns
2.4 V
 EVDD0  5.5 V
113 ns
SIp hold time (from SCKp↑)
Note 2
tKSI1 38 ns
Delay time from SCKp↓ to SOp output
Note 3
tKSO1
C = 30 pF
Note 4
50 ns