Datasheet

RL78/G14 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85 C)
R01DS0053EJ0200 Rev. 2.00 Page 101 of 187
Oct 25, 2013
Note 1. The first clock pulse is generated after this period when the start/restart condition is detected.
Note 2. The maximum value (MAX.) of tHD: DAT is during normal transfer and a wait state is inserted in the ACK (acknowledge)
timing.
Caution The values in the above table are applied even when bit 2 (PIOR02) in the peripheral I/O redirection register 0
(PIOR0) is 1. At this time, the pin characteristics (I
OH1, IOL1, VOH1, VOL1) must satisfy the values in the redirect
destination.
Note 3.
The maximum value of Cb (communication line capacitance) and the value of Rb (communication line pull-up resistor) at
that time in each mode are as follows.
Fast mode plus: C
b = 120 pF, Rb = 1.1 k
IICA serial transfer timing
Remark n = 0, 1
(3) I
2
C fast mode plus
(TA = -40 to +85 C, 1.6 V  EVDD0 = EVDD1  VDD  5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter Symbol Conditions HS (high-speed
main) mode
LS (low-speed
main) mode
LV (low-voltage
main) mode
Unit
MIN. MAX. MIN. MAX. MIN. MAX.
SCLA0 clock frequency f
SCL Fast mode plus:
f
CLK  10 MHz
2.7 V
 EVDD0  5.5 V 0 1000 — — kHz
Setup time of restart
condition
t
SU: STA 2.7 V  EVDD0  5.5 V 0.26 — — s
Hold time
Note 1
tHD: STA 2.7 V  EVDD0  5.5 V 0.26 — — s
Hold time when SCLA0 = “L” t
LOW 2.7 V  EVDD0  5.5 V 0.5 — — s
Hold time when SCLA0 = “H” t
HIGH 2.7 V  EVDD0  5.5 V 0.26 — — s
Data setup time (reception) t
SU: DAT 2.7 V  EVDD0  5.5 V 50 — — ns
Data hold time (transmission)
Note 2
tHD: DAT 2.7 V  EVDD0  5.5 V 0 0.45 — — s
Setup time of stop condition t
SU: STO 2.7 V  EVDD0  5.5 V 0.26 — — s
Bus-free time t
BUF 2.7 V  EVDD0  5.5 V 0.5 — — s
tSU: DAT
tHD: STA
Restart
condition
SCLAn
SDAAn
t
LOW
tHIGH
tSU: STA tHD: STA tSU: STO
Stop
condition
Stop
condition
Start
condition
tHD: DAT
tBUF