Datasheet

RL78/G12 3. ELECTRICAL SPECIFICATIONS (G: T

A = −40 to +105°C)

R01DS0193EJ0200 Rev.2.00

Sep 06, 2013

Page 78 of 106

(2) During communication at same potential (CSI mode) (master mode, SCKp... internal clock output)

(TA = −40 to +105°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V)

Parameter Symbol Conditions HS (high-speed main) Mode Unit

MIN. MAX.

SCKp cycle time tKCY1 tKCY1 ≥ 4/fCLK 2.7 V ≤ VDD ≤ 5.5 V 334 ns

2.4 V ≤ VDD ≤ 5.5 V 500 ns

SCKp high-/low-level width tKH1,

KL1

4.0 V ≤ V

DD ≤ 5.5 V tKCY1/2−24 ns

2.7 V ≤ VDD ≤ 5.5 V tKCY1/2−36 ns

2.4 V ≤ VDD ≤ 5.5 V tKCY1/2−76 ns

SIp setup time (to SCKp↑)

Note 1

tSIK1 4.0 V ≤ VDD ≤ 5.5 V 66 ns

2.7 V ≤ VDD ≤ 5.5 V 66 ns

2.4 V ≤ VDD ≤ 5.5 V 113 ns

SIp hold time (from SCKp↑)

Note 2

tKSI1 38 ns

Delay time from SCKp↓ to

SOp output

Note 3

KSO1 C = 30 pF

Note4

50 ns

Notes 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to

SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.

2. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from

SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.

3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output

becomes “from SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.

4. C is the load capacitance of the SCKp and SOp output lines.

Caution Select the normal input buffer for the SIp pin and the normal output mode for the SOp and SCKp pins

by using port input mode register 1 (PIM1) and port output mode registers 0, 1, 4 (POM0, POM1,

POM4).

Remarks 1. p: CSI number (p = 00, 01, 11, 20), m: Unit number (m = 0, 1), n: Channel number (n = 0, 1, 3)

2. f

MCK: Serial array unit operation clock frequency

(Operation clock to be set by the serial clock select register m (SPSm) and the CKSmn bit of serial mode