Datasheet

RL78/G12 3. ELECTRICAL SPECIFICATIONS (G: T
A = −40 to +105°C)
R01DS0193EJ0200 Rev.2.00
Sep 06, 2013
Page 85 of 106
(6) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (master mode, SCKp... internal clock
output) (1/3)
(T
A = −40 to +105°C, 2.4 V ≤ VDD ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter Symbol Conditions HS (high-speed main) Mode Unit
MIN. MAX.
SCKp cycle time tKCY1 tKCY1 ≥ 4/fCLK 4.0 V ≤ VDD ≤ 5.5 V,
2.7 V ≤ V
b ≤ 4.0 V,
C
b = 30 pF, Rb = 1.4 kΩ
600 ns
2.7 V ≤ VDD < 4.0 V,
2.3 V ≤ V
b ≤ 2.7 V,
C
b = 30 pF, Rb = 2.7 kΩ
1000 ns
2.4 V ≤ VDD < 3.3 V,
1.6 V ≤ V
b ≤ 2.0 V,
C
b = 30 pF, Rb = 5.5 kΩ
2300 ns
SCKp high-level width tKH1 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
C
b = 30 pF, Rb = 1.4 kΩ
t
KCY1/2 −150 ns
2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
C
b = 30 pF, Rb = 2.7 kΩ
t
KCY1/2 −340 ns
2.4 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,
C
b = 30 pF, Rb = 5.5 kΩ
t
KCY1/2 −916 ns
SCKp low-level width tKL1 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
C
b = 30 pF, Rb = 1.4 kΩ
t
KCY1/2 −24 ns
2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
C
b = 30 pF, Rb = 2.7 kΩ
t
KCY1/2 −36 ns
2.4 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,
C
b = 30 pF, Rb = 5.5 kΩ
t
KCY1/2 −100 ns
Cautions 1. Select the TTL input buffer for the SIp pin and the N-ch open drain output (V
DD tolerance) mode
for the SOp pin and SCKp pin by using port input mode register 1 (PIM1) and port output mode
register 1 (POM1). For V
IH and VIL, see the DC characteristics with TTL input buffer selected.
2. CSI01 and CSI11 cannot communicate at different potential.
Remarks 1. R
b [Ω]: Communication line (SCKp, SOp) pull-up resistance, Cb [F]: Communication line (SCKp, SOp)
load capacitance, V
b [V]: Communication line voltage
2. p: CSI number (p = 00, 20)