Datasheet

RL78/G12 3. ELECTRICAL SPECIFICATIONS (G: T
A = −40 to +105°C)
R01DS0193EJ0200 Rev.2.00
Sep 06, 2013
Page 87 of 106
(6) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (master mode, SCKp... internal clock
output) (3/3)
(TA = −40 to +105°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter Symbol Conditions HS (high-speed main) Mode Unit
MIN. MAX.
SIp setup time (to SCKp↓)
Note
t
SIK1
4.0 V ≤ V
DD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
C
b = 30 pF, Rb = 1.4 kΩ
88 ns
2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
C
b = 30 pF, Rb = 2.7 kΩ
88 ns
2.4 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,
C
b = 30 pF, Rb = 5.5 kΩ
220 ns
SIp hold time
(from SCKp↓)
Note
t
KSI1
4.0 V ≤ V
DD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
C
b = 30 pF, Rb = 1.4 kΩ
38 ns
2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
C
b = 30 pF, Rb = 2.7 kΩ
38 ns
2.4 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,
C
b = 30 pF, Rb = 5.5 kΩ
38 ns
Delay time from SCKp↑ to
SOp output
Note
t
KSO1
4.0 V ≤ V
DD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
C
b = 30 pF, Rb = 1.4 kΩ
50 ns
2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
C
b = 30 pF, Rb = 2.7 kΩ
50 ns
2.4 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,
C
b = 30 pF, Rb = 5.5 kΩ
50 ns
Note When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
Cautions 1. Select the TTL input buffer for the SIp pin and the N-ch open drain output (V
DD tolerance) mode
for the SOp pin and SCKp pin by using port input mode register 1 (PIM1) and port output mode
register 1 (POM1). For V
IH and VIL, see the DC characteristics with TTL input buffer selected.
2. CSI01 and CSI11 cannot communicate at different potential.
Remarks 1. R
b [Ω]: Communication line (SCKp, SOp) pull-up resistance, Cb [F]: Communication line (SCKp, SOp)
load capacitance, V
b [V]: Communication line voltage
2. p: CSI number (p = 00, 20), m: Unit number (m = 0, 1), n: Channel number (n = 0)
CSI mode connection diagram (during communication at different potential)
V b
R b
SCKp
SOp
SCK
SI
User's device
SIp
SO
V
b
R b
<Master>
RL78
microcontroller