Datasheet

RL78/G12 3. ELECTRICAL SPECIFICATIONS (G: T
A = −40 to +105°C)
R01DS0193EJ0200 Rev.2.00
Sep 06, 2013
Page 82 of 106
(5) Communication at different potential (1.8 V, 2.5 V, 3 V) (UART mode)
(TA = −40 to +105°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter Symbol Conditions
HS (high-speed main)
Mode
Unit
MIN. MAX.
Transfer
rate
Note4
Reception 4.0 V ≤ V
DD ≤ 5.5 V,
2.7 V ≤ V
b ≤ 4.0 V
f
MCK/12
Note 1
bps
Theoretical value of the maximum
transfer rate
f
MCK = fCLK
Note 2
2.0 Mbps
2.7 V ≤ VDD < 4.0 V,
2.3 V ≤ V
b ≤ 2.7 V
f
MCK/12
Note 1
bps
Theoretical value of the maximum
transfer rate
f
MCK = fCLK
Note 2
2.0 Mbps
2.4 V ≤ VDD < 3.3 V,
1.6 V ≤ V
b ≤ 2.0 V
f
MCK/12
Note 1
bps
Theoretical value of the maximum
transfer rate
f
MCK = fCLK
Note 2
2.0
Mbps
Transmission 4.0 V ≤ VDD ≤ 5.5 V,
2.7 V ≤ V
b ≤ 4.0 V
Note 3 bps
Theoretical value of the maximum
transfer rate
C
b = 50 pF, Rb = 1.4 kΩ, Vb = 2.7 V
2.0
Note 4
Mbps
2.7 V ≤ VDD < 4.0 V,
2.3 V ≤ V
b ≤ 2.7 V,
Note 5 bps
Theoretical value of the maximum
transfer rate
C
b = 50 pF, Rb = 2.7 kΩ, Vb = 2.3 V
1.2
Note 6
Mbps
2.4 V ≤ VDD < 3.3 V,
1.6 V ≤ V
b ≤ 2.0 V
Notes
2, 7
bps
Theoretical value of the maximum
transfer rate
C
b = 50 pF, Rb = 5.5 kΩ, Vb = 1.6 V
0.43
Note 8
Mbps
Notes 1. Transfer rate in the SNOOZE mode is 4800 bps only.
2. The maximum operating frequencies of the CPU/peripheral hardware clock (f
CLK) are:
HS (high-speed main) mode: 24 MHz (2.7 V ≤ V
DD ≤ 5.5 V)
16 MHz (2.4 V ≤ V
DD ≤ 5.5 V)
3. The smaller maximum transfer rate derived by using f
MCK/12 or the following expression is the valid
maximum transfer rate.
Expression for calculating the transfer rate when 4.0 V ≤ V
DD ≤ 5.5 V and 2.7 V ≤ Vb ≤ 4.0 V
Maximum transfer rate =
1
[bps]
{−C
b × Rb × ln (1 −
2.2
V
b
)} × 3
1
Transfer rate × 2
− {−Cb × Rb × ln (1 −
2.2
V
b
)}
Baud rate error (theoretical value) = × 100 [%]
(
1
Transfer rate
) × Number of transferred bits
* This value is the theoretical value of the relative difference between the transmission and reception sides.