Datasheet

RL78/G12 3. ELECTRICAL SPECIFICATIONS (G: T
A = −40 to +105°C)
R01DS0193EJ0200 Rev.2.00
Sep 06, 2013
Page 79 of 106
(3) During communication at same potential (CSI mode) (slave mode, SCKp... external clock input)
(TA = −40 to +105°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter Symbol Conditions HS (high-speed main) Mode Unit
MIN. MAX.
SCKp cycle time
Note4
tKCY2 4.0 V ≤ VDD ≤ 5.5 V 20 MHz < fMCK 16/fMCK ns
fMCK ≤ 20 MHz 12/fMCK ns
2.7 V ≤ VDD ≤ 5.5 V 16 MHz < fMCK 16/fMCK ns
fMCK ≤ 16 MHz 12/fMCK ns
2.4 V ≤ VDD ≤ 5.5 V 12/fMCK
and 1000
ns
SCKp high-/low-level width tKH2,
t
KL2
4.0 V ≤ V
DD ≤ 5.5 V tKCY2/2−14 ns
2.7 V ≤ VDD ≤ 5.5 V tKCY2/2−16 ns
2.4 V ≤ VDD ≤ 5.5 V tKCY2/2−36 ns
SIp setup time (to SCKp↑)
Note 1
t
SIK2 2.7 V ≤ VDD ≤ 5.5 V 1/fMCK + 40 ns
2.4 V ≤ VDD ≤ 5.5 V 1/fMCK + 60 ns
SIp hold time
(from SCKp↑)
Note 2
t
KSI2 1/fMCK + 62 ns
Delay time from SCKp↓ to
SOp output
Note 3
t
KSO2 C = 30 pF
Note4
2.7 V ≤ VDD ≤ 5.5 V 2/fMCK + 66 ns
2.4 V ≤ VDD ≤ 5.5 V 2/fMCK + 113 ns
Notes 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to
SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
2. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from
SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output
becomes “from SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
4. C is the load capacitance of the SOp output lines.
5. Transfer rate in the SNOOZE mode: MAX. 1 Mbps
Caution Select the normal input buffer for the SIp and SCKp pins and the normal output mode for the SOp pin
by using port input mode register 1 (PIM1) and port output mode registers 0, 1, 4 (POM0, POM1,
POM4).
CSI mode connection diagram (during communication at same potential)
RL78
microcontroller
SCKp
SOp
SCK
SI
User's device
SIp SO