Datasheet

RL78/G13 2. ELECTRICAL SPECIFICATIONS (A, D: T
A = -40 to +85°C)
Page 84 of 194R01DS0131EJ0310 Rev.3.10
Nov 15, 2013
(3) During communication at same potential (CSI mode) (master mode, SCKp... internal clock output)
(TA = −40 to +85°C, 1.6 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Notes 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to
SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
2. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from
SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output
becomes “from SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
4. C is the load capacitance of the SCKp and SOp output lines.
Caution Select the normal input buffer for the SIp pin and the normal output mode for the SOp pin and
SCKp pin by using port input mode register g (PIMg) and port output mode register g (POMg).
Parameter Symbol Conditions HS (high-speed
main) Mode
LS (low-speed
main) Mode
LV (low-voltage
main) Mode
Unit
MIN. MAX. MIN. MAX. MIN. MAX.
SCKp cycle time tKCY1 tKCY1 ≥ 4/fCLK 2.7 V ≤ EVDD0 ≤ 5.5
V
125 500 1000 ns
2.4 V ≤ EVDD0 ≤ 5.5
V
250 500 1000 ns
1.8 V ≤ EVDD0 ≤ 5.5
V
500 500 1000 ns
1.7 V ≤ EVDD0 ≤ 5.5
V
1000 1000 1000 ns
1.6 V ≤ EVDD0 ≤ 5.5
V
⎯ 1000 1000 ns
SCKp high-/low-level
width
tKH1,
t
KL1
4.0 V ≤ EV
DD0 ≤ 5.5 V tKCY1/2 −
12
tKCY1/2 −
50
tKCY1/2 −
50
ns
2.7 V ≤ EVDD0 ≤ 5.5 V tKCY1/2 −
18
tKCY1/2 −
50
tKCY1/2 −
50
ns
2.4 V ≤ EVDD0 ≤ 5.5 V tKCY1/2 −
38
tKCY1/2 −
50
tKCY1/2 −
50
ns
1.8 V ≤ EVDD0 ≤ 5.5 V tKCY1/2 −
50
tKCY1/2 −
50
tKCY1/2 −
50
ns
1.7 V ≤ EVDD0 ≤ 5.5 V tKCY1/2 −
100
tKCY1/2 −
100
tKCY1/2 −
100
ns
1.6 V ≤ EVDD0 ≤ 5.5 V ⎯ tKCY1/2 −
100
tKCY1/2 −
100
ns
SIp setup time
(to SCKp↑)
Note 1
t
SIK1 4.0 V ≤ EVDD0 ≤ 5.5 V 44 110 110 ns
2.7 V ≤ EVDD0 ≤ 5.5 V 44 110 110 ns
2.4 V ≤ EVDD0 ≤ 5.5 V 75 110 110 ns
1.8 V ≤ EVDD0 ≤ 5.5 V 110 110 110 ns
1.7 V ≤ EVDD0 ≤ 5.5 V 220 220 220 ns
1.6 V ≤ EVDD0 ≤ 5.5 V ⎯ 220 220 ns
SIp hold time
(from SCKp↑)
Note 2
t
KSI1 1.7 V ≤ EVDD0 ≤ 5.5 V 19 19 19 ns
1.6 V ≤ EVDD0 ≤ 5.5 V ⎯ 19 19 ns
Delay time from
SCKp↓ to SOp
output
Note 3
t
KSO1 1.7 V ≤ EVDD0 ≤ 5.5 V
C = 30 pF
Note 4
25 25 25 ns
1.6 V ≤ EVDD0 ≤ 5.5 V
C = 30 pF
Note 4
⎯ 25 25 ns