Datasheet

RL78/G13 2. ELECTRICAL SPECIFICATIONS (A, D: T
A = -40 to +85°C)
Page 95 of 194R01DS0131EJ0310 Rev.3.10
Nov 15, 2013
(7) Communication at different potential (2.5 V, 3 V) (CSI mode) (master mode, SCKp... internal clock output,
corresponding CSI00 only) (1/2)
(TA = −40 to +85°C, 2.7 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter Symbol Conditions HS (high-speed
main) Mode
LS (low-speed
main) Mode
LV (low-voltage
main) Mode
Unit
MIN. MAX. MIN. MAX. MIN. MAX.
SCKp cycle time tKCY1 tKCY1 ≥ 2/fCLK 4.0 V ≤ EVDD0 ≤ 5.5 V,
2.7 V ≤ V
b ≤ 4.0 V,
C
b = 20 pF, Rb = 1.4
kΩ
200 1150 1150 ns
2.7 V ≤ EVDD0 < 4.0 V,
2.3 V ≤ V
b ≤ 2.7 V,
C
b = 20 pF, Rb = 2.7
kΩ
300 1150 1150 ns
SCKp high-level
width
tKH1 4.0 V ≤ EVDD0 ≤ 5.5 V,
2.7 V ≤ V
b ≤ 4.0 V,
C
b = 20 pF, Rb = 1.4 kΩ
t
KCY1/2 −
50
tKCY1/2 −
50
tKCY1/2 −
50
ns
2.7 V ≤ EVDD0 < 4.0 V,
2.3 V ≤ V
b ≤ 2.7 V,
C
b = 20 pF, Rb = 2.7 kΩ
t
KCY1/2 −
120
tKCY1/2 −
120
tKCY1/2 −
120
ns
SCKp low-level
width
tKL1 4.0 V ≤ EVDD0 ≤ 5.5 V,
2.7 V ≤ V
b ≤ 4.0 V,
C
b = 20 pF, Rb = 1.4 kΩ
t
KCY1/2 −
7
tKCY1/2 −
50
tKCY1/2 −
50
ns
2.7 V ≤ EVDD0 < 4.0 V,
2.3 V ≤ V
b ≤ 2.7 V,
C
b = 20 pF, Rb = 2.7 kΩ
t
KCY1/2 −
10
tKCY1/2 −
50
tKCY1/2 −
50
ns
SIp setup time
(to SCKp↑)
Note 1
t
SIK1 4.0 V ≤ EVDD0 ≤ 5.5 V,
2.7 V ≤ V
b ≤ 4.0 V,
C
b = 20 pF, Rb = 1.4 kΩ
58 479 479 ns
2.7 V ≤ EVDD0 < 4.0 V,
2.3 V ≤ V
b ≤ 2.7 V,
C
b = 20 pF, Rb = 2.7 kΩ
121 479 479 ns
SIp hold time
(from SCKp↑)
Note
1
t
KSI1 4.0 V ≤ EVDD0 ≤ 5.5 V,
2.7 V ≤ V
b ≤ 4.0 V,
C
b = 20 pF, Rb = 1.4 kΩ
10 10 10 ns
2.7 V ≤ EVDD0 < 4.0 V,
2.3 V ≤ V
b ≤ 2.7 V,
C
b = 20 pF, Rb = 2.7 kΩ
10 10 10 ns
Delay time from
SCKp↓ to SOp
output
Note 1
t
KSO1 4.0 V ≤ EVDD0 ≤ 5.5 V,
2.7 V ≤ V
b ≤ 4.0 V,
C
b = 20 pF, Rb = 1.4 kΩ
60 60 60 ns
2.7 V ≤ EVDD0 < 4.0 V,
2.3 V ≤ V
b ≤ 2.7 V,
C
b = 20 pF, Rb = 2.7 kΩ
130 130 130 ns
(Notes, Caution, and Remarks are listed on the next page.)