Datasheet

RL78/G13 2. ELECTRICAL SPECIFICATIONS (A, D: T
A = -40 to +85°C)
Page 81 of 194R01DS0131EJ0310 Rev.3.10
Nov 15, 2013
2.5 Peripheral Functions Characteristics
AC Timing Test Points
VIH/VOH
VIL/VOL
Test points
V
IH/VOH
VIL/VOL
2.5.1 Serial array unit
(1) During communication at same potential (UART mode)
(T
A = −40 to +85°C, 1.6 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter Symbol Conditions HS (high-speed
main) Mode
LS (low-speed
main) Mode
LV (low-voltage
main) Mode
Unit
MIN. MAX. MIN. MAX. MIN. MAX.
Transfer rate
Note 1
2.4 V≤ EV
DD0 ≤ 5.5 V fMCK/6
Note 2
fMCK/6
f
MCK/6
bps
Theoretical value of the
maximum transfer rate
f
MCK = fCLK
Note 3
5.3 1.3 0.6 Mbps
1.8 V ≤ EVDD0 ≤ 5.5 V fMCK/6
Note 2
fMCK/6
f
MCK/6
bps
Theoretical value of the
maximum transfer rate
f
MCK = fCLK
Note 3
5.3 1.3 0.6 Mbps
1.7 V ≤ EVDD0 ≤ 5.5 V fMCK/6
Note 2
fMCK/6
Note 2
f
MCK/6
bps
Theoretical value of the
maximum transfer rate
f
MCK = fCLK
Note 3
5.3 1.3 0.6 Mbps
1.6 V ≤ EVDD0 ≤ 5.5 V ⎯ fMCK/6
Note 2
f
MCK/6
bps
Theoretical value of the
maximum transfer rate
f
MCK = fCLK
Note 3
⎯ 1.3 0.6 Mbps
Notes 1. Transfer rate in the SNOOZE mode is 4800 bps only.
2. The following conditions are required for low voltage interface when EVDD0 < VDD.
2.4 V ≤ EV
DD0 < 2.7 V : MAX. 2.6 Mbps
1.8 V ≤ EVDD0 < 2.4 V : MAX. 1.3 Mbps
1.6 V ≤ EVDD0 < 1.8 V : MAX. 0.6 Mbps
3. The maximum operating frequencies of the CPU/peripheral hardware clock (fCLK) are:
HS (high-speed main) mode: 32 MHz (2.7 V ≤ V
DD ≤ 5.5 V)
16 MHz (2.4 V ≤ VDD ≤ 5.5 V)
LS (low-speed main) mode: 8 MHz (1.8 V ≤ V
DD ≤ 5.5 V)
LV (low-voltage main) mode: 4 MHz (1.6 V ≤ V
DD ≤ 5.5 V)
Caution Select the normal input buffer for the RxDq pin and the normal output mode for the TxDq pin by
using port input mode register g (PIMg) and port output mode register g (POMg).