Datasheet

RL78/G13 2. ELECTRICAL SPECIFICATIONS (A, D: T
A = -40 to +85°C)
Page 78 of 194R01DS0131EJ0310 Rev.3.10
Nov 15, 2013
Note The following conditions are required for low voltage interface when EVDD0 < VDD
1.8 V ≤ EVDD0 < 2.7 V : MIN. 125 ns
1.6 V ≤ EVDD0 < 1.8 V : MIN. 250 ns
Remark f
MCK: Timer array unit operation clock frequency
(Operation clock to be set by the CKSmn0, CKSmn1 bits of timer mode register mn (TMRmn).
m: Unit number (m = 0, 1), n: Channel number (n = 0 to 7))
Minimum Instruction Execution Time during Main System Clock Operation
T
CY vs VDD (HS (high-speed main) mode)
1.0
0.1
0
10
1.0 2.0 3.0 4.0 5.0 6.0
5.5
2.7
0.01
2.4
0.03125
0.0625
0.05
When the high-speed on-chip oscillator clock is selected
During self programming
When high-speed system clock is selected
Cycle time TCY [µs]
Supply voltage VDD [V]