Datasheet

RL78/G13 2. ELECTRICAL SPECIFICATIONS (A, D: T
A = -40 to +85°C)
Page 60 of 194R01DS0131EJ0310 Rev.3.10
Nov 15, 2013
(TA = −40 to +85°C, 1.6 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (3/5)
Items Symbol Conditions MIN. TYP. MAX. Unit
Input voltage,
high
VIH1 P00 to P07, P10 to P17, P30 to P37,
P40 to P47, P50 to P57, P64 to P67,
P70 to P77, P80 to P87, P90 to P97,
P100 to P106, P110 to P117, P120,
P125 to P127, P140 to P147
Normal input buffer 0.8EV
DD0 EVDD0 V
VIH2 P01, P03, P04, P10, P11,
P13 to P17, P43, P44, P53 to P55,
P80, P81, P142, P143
TTL input buffer
4.0 V
≤ EV DD0 ≤ 5.5 V
2.2 EVDD0 V
TTL input buffer
3.3 V
≤ EV DD0 < 4.0 V
2.0 EVDD0 V
TTL input buffer
1.6 V
≤ EV DD0 < 3.3 V
1.5 EVDD0 V
VIH3 P20 to P27, P150 to P156 0.7VDD VDD V
VIH4 P60 to P63 0.7EVDD0 6.0 V
VIH5 P121 to P124, P137, EXCLK, EXCLKS, RESET 0.8VDD VDD V
Input voltage,
low
VIL1 P00 to P07, P10 to P17, P30 to P37,
P40 to P47, P50 to P57, P64 to P67,
P70 to P77, P80 to P87, P90 to P97,
P100 to P106, P110 to P117, P120,
P125 to P127, P140 to P147
Normal input buffer 0 0.2EV
DD0 V
VIL2 P01, P03, P04, P10, P11,
P13 to P17, P43, P44, P53 to P55,
P80, P81, P142, P143
TTL input buffer
4.0 V
≤ EV DD0 ≤ 5.5 V
0 0.8 V
TTL input buffer
3.3 V
≤ EV DD0 < 4.0 V
0 0.5 V
TTL input buffer
1.6 V
≤ EV DD0 < 3.3 V
0 0.32 V
VIL3 P20 to P27, P150 to P156 0 0.3VDD V
VIL4 P60 to P63 0 0.3EVDD0 V
VIL5 P121 to P124, P137, EXCLK, EXCLKS, RESET 0 0.2VDD V
Caution The maximum value of VIH of pins P00, P02 to P04, P10 to P15, P17, P43 to P45, P50, P52 to P55,
P71, P74, P80 to P82, P96, and P142 to P144 is EVDD0, even in the N-ch open-drain mode.
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the
port pins.