Datasheet

RL78/G13 3. ELECTRICAL SPECIFICATIONS (G: T
A = -40 to +105°C)
Page 165 of 194R01DS0131EJ0310 Rev.3.10
Nov 15, 2013
Simplified I
2
C mode connection diagram (during communication at different potential)
SDAr
SCLr
SDA
SCL
User device
V
b
R b
V b
R b
RL78
microcontroller
Simplified I
2
C mode serial transfer timing (during communication at different potential)
SDAr
t
LOW
t HIGH
t HD:DAT
SCLr
t
SU:DAT
1/f SCL
Caution Select the TTL input buffer and the N-ch open drain output (V
DD tolerance (When 20- to 52-pin
products)/EVDD tolerance (When 64- to 100-pin products)) mode for the SDAr pin and the N-ch
open drain output (VDD tolerance (When 20- to 52-pin products)/EVDD tolerance (When 64- to 100-
pin products)) mode for the SCLr pin by using port input mode register g (PIMg) and port output
mode register g (POMg). For V
IH and VIL, see the DC characteristics with TTL input buffer selected.
Remarks 1. R
b[Ω]:Communication line (SDAr, SCLr) pull-up resistance, Cb[F]: Communication line (SDAr, SCLr)
load capacitance, V
b[V]: Communication line voltage
2. r: IIC number (r = 00, 01, 10, 20, 30, 31), g: PIM, POM number (g = 0, 1, 4, 5, 8, 14)
3. f
MCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number,
n: Channel number (mn = 00, 01, 02, 10, 12, 13)