Datasheet

RL78/G13 3. ELECTRICAL SPECIFICATIONS (G: T
A = -40 to +105°C)
Page 160 of 194R01DS0131EJ0310 Rev.3.10
Nov 15, 2013
(7) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (slave mode, SCKp... external clock
input)
(T
A = −40 to +105°C, 2.4 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter Symbol Conditions HS (high-speed main) Mode Unit
MIN. MAX.
SCKp cycle time
Note 1
t
KCY2 4.0 V ≤ EV DD0 ≤ 5.5
V,
2.7 V
≤ V b ≤ 4.0 V
24 MHz < f
MCK 28/fMCK ns
20 MHz < fMCK ≤ 24 MHz 24/fMCK ns
8 MHz < fMCK ≤ 20 MHz 20/fMCK ns
4 MHz < fMCK ≤ 8 MHz 16/fMCK ns
fMCK ≤ 4 MHz 12/fMCK ns
2.7 V ≤ EV DD0 < 4.0
V,
2.3 V
≤ V b ≤ 2.7 V
24 MHz < f
MCK 40/fMCK ns
20 MHz < fMCK ≤ 24 MHz 32/fMCK ns
16 MHz < fMCK ≤ 20 MHz 28/fMCK ns
8 MHz < fMCK ≤ 16 MHz 24/fMCK ns
4 MHz < fMCK ≤ 8 MHz 16/fMCK ns
fMCK ≤ 4 MHz 12/fMCK ns
2.4 V ≤ EV DD0 < 3.3
V,
1.6 V
≤ V b ≤ 2.0 V
24 MHz < f
MCK 96/fMCK ns
20 MHz < fMCK ≤ 24 MHz 72/fMCK ns
16 MHz < fMCK ≤ 20 MHz 64/fMCK ns
8 MHz < fMCK ≤ 16 MHz 52/fMCK ns
4 MHz < fMCK ≤ 8 MHz 32/fMCK ns
fMCK ≤ 4 MHz 20/fMCK ns
SCKp high-/low-level
width
tKH2,
t
KL2
4.0 V ≤ EV
DD0 ≤ 5.5 V,
2.7 V ≤ V
b ≤ 4.0 V
t KCY2/2 − 24 ns
2.7 V ≤ EVDD0 < 4.0 V,
2.3 V ≤ V
b ≤ 2.7 V
t KCY2/2 − 36 ns
2.4 V ≤ EVDD0 < 3.3 V,
1.6 V ≤ V
b ≤ 2.0 V
Note 2
t KCY2/2 − 100 ns
SIp setup time
(to SCKp↑)
Note2
t
SIK2 4.0 V ≤ EVDD0 ≤ 5.5 V,
2.7 V ≤ V
b ≤ 4.0 V
1/f
MCK + 40 ns
2.7 V ≤ EVDD0 < 4.0 V,
2.3 V ≤ V
b ≤ 2.7 V
1/f
MCK + 40 ns
2.4 V ≤ EVDD0 < 3.3 V,
1.6 V ≤ V
b ≤ 2.0 V
1/f
MCK + 60 ns
SIp hold time
(from SCKp↑)
Note 3
t
KSI2 1/fMCK + 62 ns
Delay time from SCKp↓
to SOp output
Note 4
t
KSO2 4.0 V ≤ EVDD0 ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
C
b = 30 pF, Rb = 1.4 kΩ
2/f
MCK + 240 ns
2.7 V ≤ EVDD0 < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
C
b = 30 pF, Rb = 2.7 kΩ
2/f
MCK + 428 ns
2.4 V ≤ EVDD0 < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V
C
b = 30 pF, Rb = 5.5 kΩ
2/f
MCK + 1146 ns
(Notes, Caution and Remarks are listed on the next page.)