Datasheet

RL78/G13 3. ELECTRICAL SPECIFICATIONS (G: T
A = -40 to +105°C)
Page 149 of 194R01DS0131EJ0310 Rev.3.10
Nov 15, 2013
(4) During communication at same potential (simplified I
2
C mode)
(TA = −40 to +105°C, 2.4 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter Symbol Conditions HS (high-speed main)
Mode
Unit
MIN. MAX.
SCLr clock frequency fSCL
2.7 V ≤ EV
DD0 ≤ 5.5 V,
C
b = 50 pF, Rb = 2.7 kΩ
400
Note1
kHz
2.4 V ≤ EVDD0 ≤ 5.5 V,
C
b = 100 pF, Rb = 3 kΩ
100
Note1
kHz
Hold time when SCLr = “L” tLOW
2.7 V ≤ EV
DD0 ≤ 5.5 V,
C
b = 50 pF, Rb = 2.7 kΩ
1200 ns
2.4 V ≤ EVDD0 ≤ 5.5 V,
C
b = 100 pF, Rb = 3 kΩ
4600 ns
Hold time when SCLr = “H” tHIGH
2.7 V ≤ EV
DD0 ≤ 5.5 V,
C
b = 50 pF, Rb = 2.7 kΩ
1200 ns
2.4 V ≤ EVDD0 ≤ 5.5 V,
C
b = 100 pF, Rb = 3 kΩ
4600 ns
Data setup time (reception) tSU:DAT
2.7 V ≤ EV
DD0 ≤ 5.5 V,
C
b = 50 pF, Rb = 2.7 kΩ
1/f
MCK + 220
Note2
ns
2.4 V ≤ EVDD0 ≤ 5.5 V,
C
b = 100 pF, Rb = 3 kΩ
1/f
MCK + 580
Note2
ns
Data hold time (transmission) tHD:DAT
2.7 V ≤ EV
DD0 ≤ 5.5 V,
C
b = 50 pF, Rb = 2.7 kΩ
0 770 ns
2.4 V ≤ EVDD0 ≤ 5.5 V,
C
b = 100 pF, Rb = 3 kΩ
0 1420 ns
Notes 1. The value must also be equal to or less than fMCK/4.
2. Set the f
MCK value to keep the hold time of SCLr = "L" and SCLr = "H".
Caution Select the normal input buffer and the N-ch open drain output (VDD tolerance (When 20- to 52-pin
products)/EV
DD tolerance (When 64- to 100-pin products)) mode for the SDAr pin and the normal
output mode for the SCLr pin by using port input mode register g (PIMg) and port output mode
register h (POMh).
(Remarks are listed on the next page.)